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Disambiguation of "Friedman, Daniel J."

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A 78mW 11.1Gb/s 5-tap DFE receiver with digitally calibrated current-integrating summers in 65nm CMOS.

, , , , , , , and . ISSCC, page 368-369. IEEE, (2009)

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Zviel Friedman

Alexander Friedman

Ariell Friedman

Michel Friedman

Daniel J Schad

 

Other publications of authors with the same name

7.2 A 28GHz 32-element phased-array transceiver IC with concurrent dual polarized beams and 1.4 degree beam-steering resolution for 5G communication., , , , , , , , , and 10 other author(s). ISSCC, page 128-129. IEEE, (2017)A 1.8 pJ/bit 16×16Gb/s Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link Recalibration., , , , , , , , , and . IEEE J. Solid State Circuits, 51 (8): 1744-1755 (2016)SiGe BiCMOS integrated circuits for high-speed serial communication links., , , , , , , , , and 2 other author(s). IBM J. Res. Dev., 47 (2-3): 259-282 (2003)A wide tuning range (1 GHz-to-15 GHz) fractional-N all-digital PLL in 45nm SOI., , , , and . CICC, page 431-434. IEEE, (2008)An Integral Path Self-Calibration Scheme for a Dual-Loop PLL., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 48 (4): 996-1008 (2013)A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology., , , , , , , , , and 5 other author(s). IEEE J. Solid State Circuits, 41 (12): 2885-2900 (2006)A 0.18-μm SiGe BiCMOS receiver and transmitter chipset for SONET OC-768 transmission systems., , , , and . IEEE J. Solid State Circuits, 38 (12): 2147-2154 (2003)Indirect Performance Sensing for On-Chip Self-Healing of Analog and RF Circuits., , , , , , , , , and 4 other author(s). IEEE Trans. Circuits Syst. I Regul. Pap., 61-I (8): 2243-2252 (2014)Ultra-low-power analog design.. ISSCC, page 526-527. IEEE, (2017)All-Digital Dynamic Self-Detection and Self-Compensation of Static Phase Offsets in Charge-Pump PLLs., , , and . ISSCC, page 176-595. IEEE, (2007)