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A 975-mW Fully Integrated Genetic Variant Discovery System-on-Chip in 28 nm for Next-Generation Sequencing.

Y. Wu, Y. Chen, C. Yang, C. Lee, C. Yu, N. Chang, L. Chen, J. Chang, C. Lin, H. Chen, C. Chen, J. Hung, and C. Yang. IEEE J. Solid State Circuits, 56 (1): 123-135 (2021)

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Tze-Lung Chen

Yen-Chih Chen

Yen-Ta Chen

Shing-lung Chen

Chen-Shyong Yen

Other publications of authors with the same name

Neural Network Training With Stochastic Hardware Models and Software Abstractions.B. Zhang, L. Chen, and N. Verma. IEEE Trans. Circuits Syst. I Regul. Pap., 68 (4): 1532-1542 (2021)A fast heuristic approach for parametric yield enhancement of analog designs.C. Liu, Y. Chen, C. Kuo, and I. Tsai. ACM Trans. Design Autom. Electr. Syst., 17 (3): 35:1-35:20 (2012)Simultaneous optimization for low dropout regulator and its error amplifier with process variation.Y. Chen, G. Chu, Y. Lien, C. Lee, and C. Liu. VLSI-DAT, page 1-4. IEEE, (2014)Stochastic Data-driven Hardware Resilience to Efficiently Train Inference Models for Stochastic Hardware Implementations.B. Zhang, L. Chen, and N. Verma. ICASSP, page 1388-1392. IEEE, (2019)A Fully Integrated End-to-End Genome Analysis Accelerator for Next-Generation Sequencing.Y. Chen, C. Yang, Y. Wu, C. Lee, W. Chen, L. Lin, N. Chang, C. Lin, C. Chen, J. Hung and 1 other author(s). ISSCC, page 44-45. IEEE, (2023)A 3-D IC for Mitigating Energy of Memory Accessing and Data Movement in Accelerator- Based Streaming Architectures.L. Chen, S. Tao, and N. Verma. IEEE J. Solid State Circuits, 54 (6): 1778-1788 (2019)REscope: High-dimensional Statistical Circuit Simulation towards Full Failure Region Coverage.W. Wu, W. Xu, R. Krishnan, Y. Chen, and L. He. DAC, page 82:1-82:6. ACM, (2014)21.1 A Fully Integrated Genetic Variant Discovery SoC for Next-Generation Sequencing.Y. Wu, Y. Chen, C. Yang, C. Lee, C. Yu, N. Chang, L. Chen, J. Chang, C. Lin, H. Chen and 3 other author(s). ISSCC, page 322-324. IEEE, (2020)Layout-aware analog synthesis environment with yield consideration.H. Chang, Y. Chen, C. Yeh, and C. Liu. ISQED, page 589-593. IEEE, (2015)Automatic circuit sizing technique for the analog circuits with flexible TFTs considering process variation and bending effects.Y. Chen, W. Wu, G. Lu, and C. Liu. DATE, page 1458-1461. EDA Consortium San Jose, CA, USA / ACM DL, (2013)

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Disambiguation of "Chen, Yen-Lung"

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A 975-mW Fully Integrated Genetic Variant Discovery System-on-Chip in 28 nm for Next-Generation Sequencing.

Please choose a person to relate this publication to

Tze-Lung Chen

Yen-Chih Chen

Yen-Ta Chen

Shing-lung Chen

Chen-Shyong Yen

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Chen, Yen-Lung"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 975-mW Fully Integrated Genetic Variant Discovery System-on-Chip in 28 nm for Next-Generation Sequencing.

Please choose a person to relate this publication to

Tze-Lung Chen

Yen-Chih Chen

Yen-Ta Chen

Shing-lung Chen

Chen-Shyong Yen

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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MSOffice XML

A 975-mW Fully Integrated Genetic Variant Discovery System-on-Chip in 28 nm for Next-Generation Sequencing.