( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
Design of Routing-Constrained Low Power Scan Chains.

, , , , , и . DELTA, стр. 287-294. IEEE Computer Society, (2004)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Daniel Lois

Lois Hoegl

Christos Lois

Lois Hopfgartner

Gertraude Loisch-Langer

 

Другие публикации лиц с тем же именем

Power-Driven Routing-Constrained Scan Chain Design., , , , и . J. Electron. Test., 20 (6): 647-660 (2004)Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption., , , и . Asian Test Symposium, стр. 89-94. IEEE Computer Society, (1999)Low Power BIST by Filtering Non-Detecting Vectors., , , , , , , , , и . J. Electron. Test., 16 (3): 193-202 (2000)Low power BIST by filtering non-detecting vectors., , , , , , , , , и . ETW, стр. 165-170. IEEE Computer Society, (1999)A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores., , , , и . Asian Test Symposium, стр. 253-258. IEEE Computer Society, (2001)A Modified Clock Scheme for a Low Power BIST Test Pattern Generator., , , , и . VTS, стр. 306-311. IEEE Computer Society, (2001)Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity., , , , , , , и . ISCAS (1), стр. 110-113. IEEE, (1999)A Test Vector Ordering Technique for Switching Activity Reduction During Test Operation., , , и . Great Lakes Symposium on VLSI, стр. 24-. IEEE Computer Society, (1999)Integrating DFT in the Physical Synthesis Flow., , , , и . ITC, стр. 788-795. IEEE Computer Society, (2002)Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint., , , , и . ITC, стр. 488-493. IEEE Computer Society, (2003)