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Analog Integrated Circuit Topology Synthesis With Deep Reinforcement Learning.

, and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (12): 5138-5151 (2022)

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Efficient Performance Modeling for Automated CMOS Analog Circuit Synthesis., and . IEEE Trans. Very Large Scale Integr. Syst., 29 (11): 1824-1837 (2021)Deep Reinforcement Learning for Analog Circuit Structure Synthesis., and . DATE, page 1157-1160. IEEE, (2022)Signal-Division-Aware Analog Circuit Topology Synthesis Aided by Transfer Learning., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (11): 3481-3490 (November 2023)Deep Reinforcement Learning for Analog Circuit Sizing., and . ISCAS, page 1-5. IEEE, (2020)Analog Integrated Circuit Topology Synthesis With Deep Reinforcement Learning., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (12): 5138-5151 (2022)Fogging-Effect-Aware Mixed-Signal IC Placement with Reinforcement Learning., , , and . ISCAS, page 2895-2899. IEEE, (2022)Reinforcement-Learning-based Mixed-Signal IC Placement for Fogging Effect Control., , , and . ISQED, page 127-132. IEEE, (2022)Graph-Grammar-Based Analog Circuit Topology Synthesis., and . ISCAS, page 1-5. IEEE, (2019)Advanced Transitive-Closure-Graph-Based Placement Representation for Analog Layout Design., , , and . ICECS, page 1-4. IEEE, (2020)An Automated Topology Synthesis Framework for Analog Integrated Circuits., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (12): 4325-4337 (2020)