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Disambiguation of "Villamón, Francisco Gilabert"

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Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints.

, , , , , and . CISIS, page 681-687. IEEE Computer Society, (2009)

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Roger Gilabert-Oriol

Francisco Gaona

Francisco Castellanos

Francisco Cardiel

Francisco Garcés

 

Other publications of authors with the same name

EST2uni: an open, parallel tool for automated EST analysis and database creation, with a data mining web interface and microarray expression data integration., , , , , and . BMC Bioinform., (2008)Contrasting topologies for regular interconnection networks under the constraints of nanoscale silicon technology., , , , and . NoCArc@MICRO, page 37-42. ACM, (2010)Assessing fat-tree topologies for regular network-on-chip design under nanoscale technology constraints., , , , , , , and . DATE, page 562-565. IEEE, (2009)Networks-on-Chip: an Interconnect Fabric for Multiprocessor Systems-on-Chip., , , and . Embedded Systems Design and Verification, CRC Press, (2009)Exploring High-Dimensional Topologies for NoC Design Through an Integrated Analysis and Synthesis Framework., , , , , , and . NOCS, page 107-116. IEEE Computer Society, (2008)Deterministic versus Adaptive Routing in Fat-Trees., , , , and . IPDPS, page 1-8. IEEE, (2007)On the Influence of the Selection Function on the Performance of Fat-Trees., , , and . Euro-Par, volume 4128 of Lecture Notes in Computer Science, page 864-873. Springer, (2006)Enabling power efficiency through dynamic rerouting on-chip., , , , , and . ACM Trans. Embed. Comput. Syst., 12 (4): 111:1-111:23 (2013)A HoL-blocking aware mechanism for selecting the upward path in fat-tree topologies., , , , and . J. Supercomput., 71 (7): 2339-2364 (2015)Beyond Fat-tree: Unidirectional Load--Balanced Multistage Interconnection Network., , , , and . IEEE Comput. Archit. Lett., 7 (2): 49-52 (2008)