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s High-Speed IO Rate.

D. Kim, H. Kim, S. Yun, Y. Song, J. Kim, S. Joe, K. Kang, J. Jang, H. Yoon, K. Lee, M. Kim, J. Kwon, J. Jo, S. Park, J. Park, J. Cho, S. Park, G. Kim, J. Bang, H. Kim, J. Park, D. Lee, S. Lee, H. Jang, H. Lee, D. Shin, J. Park, J. Kim, J. Kim, K. Jang, I. Park, S. Moon, M. Choi, P. Kwak, J. Park, Y. Choi, S. Kim, S. Lee, D. Kang, J. Lim, D. Byeon, K. Song, J. Choi, S. Hwang, and J. Jeong. ISSCC, page 218-220. IEEE, (2020)

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Ki Hyun Yoon

Hyun-Yoon Shin

Woo-Hyun Yoon

Hee Hyun

Tae Kyung Hyun

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A 512-Gb 3-b/Cell 64-Stacked WL 3-D-NAND Flash Memory.C. Kim, D. Kim, W. Jeong, H. Kim, I. Park, H. Park, J. Lee, J. Park, Y. Ahn, J. Lee and 20 other author(s). IEEE J. Solid State Circuits, 53 (1): 124-133 (2018)19.5 Three-dimensional 128Gb MLC vertical NAND Flash-memory with 24-WL stacked layers and 50MB/s high-speed programming.K. Park, J. Han, D. Kim, S. Nam, K. Choi, M. Kim, P. Kwak, D. Lee, Y. Choi, K. Kang and 35 other author(s). ISSCC, page 334-335. IEEE, (2014)A 128 Gb 3b/cell V-NAND Flash Memory With 1 Gb/s I/O Rate.W. Jeong, J. Im, D. Kim, S. Nam, D. Shim, M. Choi, H. Yoon, D. Kim, Y. Kim, H. Park and 19 other author(s). IEEE J. Solid State Circuits, 51 (1): 204-212 (2016)A new 3-bit programming algorithm using SLC-to-TLC migration for 8MB/s high performance TLC NAND flash memory.S. Shin, D. Shim, J. Jeong, O. Kwon, S. Yoon, M. Choi, T. Kim, H. Park, H. Yoon, Y. Song and 7 other author(s). VLSIC, page 132-133. IEEE, (2012)A 1Tb 3b/Cell 8th-Generation 3D-NAND Flash Memory with 164MB/s Write Throughput and a 2.4Gb/s Interface.M. Kim, S. Yun, J. Park, H. Park, J. Lee, Y. Kim, D. Na, S. Choi, Y. Song, J. Lee and 24 other author(s). ISSCC, page 136-137. IEEE, (2022)11.4 A 512Gb 3b/cell 64-stacked WL 3D V-NAND flash memory.C. Kim, J. Cho, W. Jeong, I. Park, H. Park, D. Kim, D. Kang, S. Lee, J. Lee, W. Kim and 34 other author(s). ISSCC, page 202-203. IEEE, (2017)7.2 A 128Gb 3b/cell V-NAND flash memory with 1Gb/s I/O rate.J. Im, W. Jeong, D. Kim, S. Nam, D. Shim, M. Choi, H. Yoon, D. Kim, Y. Kim, H. Park and 24 other author(s). ISSCC, page 1-3. IEEE, (2015)Three-Dimensional 128 Gb MLC Vertical nand Flash Memory With 24-WL Stacked Layers and 50 MB/s High-Speed Programming.K. Park, S. Nam, D. Kim, P. Kwak, D. Lee, Y. Choi, M. Choi, D. Kwak, D. Kim, M. Kim and 20 other author(s). IEEE J. Solid State Circuits, 50 (1): 204-213 (2015)A 7MB/s 64Gb 3-bit/cell DDR NAND flash memory in 20nm-node technology.K. Park, O. Kwon, S. Yoon, M. Choi, I. Kim, B. Kim, M. Kim, Y. Choi, S. Shin, Y. Song and 19 other author(s). ISSCC, page 212-213. IEEE, (2011)13.1 A 1Tb 4b/cell NAND Flash Memory with tPROG=2ms, tR=110µs and 1.2Gb/s High-Speed IO Rate.D. Kim, H. Kim, S. Yun, Y. Song, J. Kim, S. Joe, K. Kang, J. Jang, H. Yoon, K. Lee and 35 other author(s). ISSCC, page 218-220. IEEE, (2020)

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Disambiguation of "Yoon, Hyun-Jun"

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13.1 A 1Tb 4b/cell NAND Flash Memory with tPROG=2ms, tR=110µs and 1.2Gb/s High-Speed IO Rate.

Please choose a person to relate this publication to

Ki Hyun Yoon

Hyun-Yoon Shin

Woo-Hyun Yoon

Hee Hyun

Tae Kyung Hyun

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Yoon, Hyun-Jun"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML 13.1 A 1Tb 4b/cell NAND Flash Memory with tPROG=2ms, tR=110µs and 1.2Gb/s High-Speed IO Rate.

Please choose a person to relate this publication to

Ki Hyun Yoon

Hyun-Yoon Shin

Woo-Hyun Yoon

Hee Hyun

Tae Kyung Hyun

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

13.1 A 1Tb 4b/cell NAND Flash Memory with tPROG=2ms, tR=110µs and 1.2Gb/s High-Speed IO Rate.