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Hardware architecture and VLSI implementation of a low-power high-performance polyphase channelizer with applications to subband adaptive filtering., , , , , , and . ICASSP (5), page 97-100. IEEE, (2004)High-performance low-power dual transition preferentially sized (DTPS) logic., and . IEEE J. Solid State Circuits, 40 (2): 480-484 (2005)13.2 A 1Tb 4b/Cell 96-Stacked-WL 3D NAND Flash Memory with 30MB/s Program Throughput Using Peripheral Circuit Under Memory Cell Array Technique., , , , , , , , , and 20 other author(s). ISSCC, page 220-221. IEEE, (2020)Low Power Adder with Adaptive Supply Voltage., , and . ICCD, page 103-106. IEEE Computer Society, (2003)7.2 A 128Gb 3b/cell V-NAND flash memory with 1Gb/s I/O rate., , , , , , , , , and 24 other author(s). ISSCC, page 1-3. IEEE, (2015)7.1 256Gb 3b/cell V-NAND flash memory with 48 stacked WL layers., , , , , , , , , and 20 other author(s). ISSCC, page 130-131. IEEE, (2016)A 128 Gb 3b/cell V-NAND Flash Memory With 1 Gb/s I/O Rate., , , , , , , , , and 19 other author(s). IEEE J. Solid State Circuits, 51 (1): 204-212 (2016)256 Gb 3 b/Cell V-nand Flash Memory With 48 Stacked WL Layers., , , , , , , , , and 19 other author(s). IEEE J. Solid State Circuits, 52 (1): 210-217 (2017)Low-power carry-select adder using adaptive supply voltage based on input vector patterns., , and . ISLPED, page 313-318. ACM, (2004)High performance and low power FIR filter design based on sharing multiplication., , , , , and . ISLPED, page 295-300. ACM, (2002)