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Disambiguation of "Chakrabarti, Chaitali"

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Compressing LSTM Networks with Hierarchical Coarse-Grain Sparsity.

, , , , and . INTERSPEECH, page 21-25. ISCA, (2020)

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Chaitali Chakrabarti

Subhadip Chakrabarti

Gopa Chakrabarti

Romon Chakrabarti

Sudhir Kumar Chakrabarti

 

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Articulation constrained learning with application to speech emotion recognition., , , , and . EURASIP J. Audio Speech Music. Process., (2019)Versa: A 36-Core Systolic Multiprocessor With Dynamically Reconfigurable Interconnect and Memory., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 57 (4): 986-998 (2022)Impact of On-chip Interconnect on In-memory Acceleration of Deep Neural Networks., , , , , and . ACM J. Emerg. Technol. Comput. Syst., 18 (2): 34:1-34:22 (2022)Impact of On-Chip Interconnect on In-Memory Acceleration of Deep Neural Networks., , , , , and . CoRR, (2021)Automated Parallel Kernel Extraction from Dynamic Application Traces., , and . CoRR, (2020)T-BFA: Targeted Bit-Flip Adversarial Weight Attack., , , , , and . IEEE Trans. Pattern Anal. Mach. Intell., 44 (11): 7928-7939 (2022)Communication and Computation Reduction for Split Learning using Asynchronous Training., , and . SiPS, page 76-81. IEEE, (2021)Data storage time sensitive ECC schemes for MLC NAND Flash memories., , , and . ICASSP, page 2513-2517. IEEE, (2013)Minimizing Area and Energy of Deep Learning Hardware Design Using Collective Low Precision and Structured Compression., , , , , and . CoRR, (2018)High sample rate array architectures for median filters.. IEEE Trans. Signal Process., 42 (3): 707-712 (1994)