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Replacing eFlash with STTRAM in IoTs: Security Challenges and Solutions.

, , , and . J. Hardw. Syst. Secur., 1 (4): 328-339 (2017)

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Priority Based Error Correction Code (ECC) for the Embedded SRAM Memories in H.264 System., , , and . J. Signal Process. Syst., 73 (2): 123-136 (2013)Adaptive Clock Generation Technique for Variation-Aware Subthreshold Logics., , and . IEEE Trans. Circuits Syst. II Express Briefs, 59-II (9): 587-591 (2012)FTFD: an informatics pipeline supporting phylogenomic analysis of fungal transcription factors., , , , , , , , , and 5 other author(s). Bioinform., 24 (7): 1024-1025 (2008)Domain wall memory based digital signal processors for area and energy-efficiency., , , and . DAC, page 64:1-64:6. ACM, (2015)Domain Wall Memory based Convolutional Neural Networks for Bit-width Extendability and Energy-Efficiency., , and . ISLPED, page 332-337. ACM, (2016)Spin Orbit Torque Device based Stochastic Multi-bit Synapses for On-chip STDP Learning., , and . ISLPED, page 21:1-21:6. ACM, (2018)Low Cost Hardware Implementation of LEA-128 Encryption using Bit-Serial Technique., , and . ISOCC, page 46-47. IEEE, (2018)Energy-efficient Hardware Architecture and VLSI Implementation of a Polyphase Channelizer with Applications to Subband Adaptive Filtering., , , , , , and . J. Signal Process. Syst., 58 (2): 125-137 (2010)Bit Parallel 6T SRAM In-memory Computing with Reconfigurable Bit-Precision., , , , and . DAC, page 1-6. IEEE, (2020)Low Area and Low Power Threshold Implementation Design Technique for AES S-Box., , and . IEEE Trans. Circuits Syst. II Express Briefs, 70 (3): 1169-1173 (March 2023)