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Disambiguation of "Zergainoh, Nacer-Eddine"

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Scheduler implementation in MP SoC design.

, , , , and . ASP-DAC, page 151-156. ACM Press, (2005)

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Nour-Eddine Zine-Eddine

Mehdi Ahmed-Nacer

Abdel-Nacer Zeghbib

Nour-Eddine Omrani

Seif-Eddine Benkabou

 

Other publications of authors with the same name

A Framework for Scalable TSV Assignment and Selection in Three-Dimensional Networks-on-Chips., , , and . VLSI Design, (2017)Scheduling with accurate communication delay model and scheduler implementation for multiprocessor system-on-chip., , , , and . Des. Autom. Embed. Syst., 11 (2-3): 167-191 (2007)Low Runtime-Overhead Software Synthesis for Communicating Concurrent Processes., , , and . IEEE International Workshop on Rapid System Prototyping, page 195-201. IEEE Computer Society, (2007)Automatic delay correction method for IP block-based design of VLSI dedicated digital signal processing systems: theoretical foundations and implementation., , and . IEEE Trans. Very Large Scale Integr. Syst., 14 (4): 349-360 (2006)Using Error Correcting Codes Without Speed Penalty in Embedded Memories: Algorithm, Implementation and Case Study., , and . J. Electron. Test., 29 (3): 383-400 (2013)A generic and high-level model of large unreliable NoCs for fault tolerance and performance analysis., , and . ETS, page 1-2. IEEE, (2014)X-Ray Fault Injection: Reviewing Defensive Approaches from a Security Perspective., , and . DFT, page 1-4. IEEE, (2022)Variability-aware task mapping strategies for many-cores processor chips., , , and . IOLTS, page 55-60. IEEE Computer Society, (2011)A new approach to deadlock-free fully adaptive routing for high-performance fault-tolerant NoCs., , and . DFT, page 121-126. IEEE Computer Society, (2016)Eliminating speed penalty in ECC protected memories., , and . DATE, page 1614-1619. IEEE, (2011)