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In-place LUT polarity inVersion to mitigate soft errors for FPGAs., , , и . DFT, стр. 81-86. IEEE Computer Society, (2016)Low power scheduling method using multiple supply voltages., , , и . ISCAS, IEEE, (2006)Fault modeling and characteristics of SRAM-based FPGAs (abstract only)., , , , , и . FPGA, стр. 279. ACM, (2011)Quantitative SEU Fault Evaluation for SRAM-Based FPGA Architectures and Synthesis Algorithms., , , , , , , и . FPL, стр. 282-285. IEEE Computer Society, (2011)In-Place FPGA Retiming for Mitigation of Variational Single-Event Transient Faults., , , , , , и . IEEE Trans. Circuits Syst. I Regul. Pap., 58-I (6): 1372-1381 (2011)SEU fault evaluation and characteristics for SRAM-based FPGA architectures and synthesis algorithms., , , , , и . ACM Trans. Design Autom. Electr. Syst., 18 (1): 13:1-13:18 (2012)In-place decomposition for robustness in FPGA., , и . ICCAD, стр. 143-148. IEEE, (2010)Fault-tolerant resynthesis with dual-output LUTs., , , , и . ASP-DAC, стр. 325-330. IEEE, (2010)RALF: Reliability Analysis for Logic Faults - An exact algorithm and its applications., , , , и . DATE, стр. 783-788. IEEE Computer Society, (2010)Heterogeneous configuration memory scrubbing for soft error mitigation in FPGAs., , , , , , и . FPT, стр. 23-28. IEEE, (2012)