( en | de | ru )

 

Disambiguation of "Fukuoka, Kazuki"

Author of the publication

copydeleteadd this publication to your clipboard
A technique for high-speed circuits on SOI using look-ahead type active body bias control.

, , , , , and . ISCAS (2), page 405-408. IEEE, (2004)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

No persons found for author name Fukuoka, Kazuki
add a person with the name Fukuoka, Kazuki
 

Other publications of authors with the same name

Testability improvement for 12.8 GB/s Wide IO DRAM controller by small area pre-bonding TSV tests and a 1 GHz sampled fully digital noise monitor., , , , , , , , , and 3 other author(s). CICC, page 1-4. IEEE, (2013)A 123μW standby power technique with EM-tolerant 1.8V I/O NMOS power switch in 28nm HKMG technology., , , , , , , , , and 1 other author(s). CICC, page 1-4. IEEE, (2012)A 28 nm High-k/MG Heterogeneous Multi-Core Mobile Application Processor With 2 GHz Cores and Low-Power 1 GHz Cores., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 50 (1): 92-101 (2015)Power-Management Features of R-Mobile U2, an Integrated Application Processor and Baseband Processor., , , , , , , , , and 5 other author(s). IEEE Micro, 33 (6): 26-36 (2013)Leakage power reduction for clock gating scheme on PD-SOI., , , , and . ISCAS (2), page 613-616. IEEE, (2004)10.2 A 28nm HPM heterogeneous multi-core mobile application processor with 2GHz cores and low-power 1GHz cores., , , , , , , , , and 4 other author(s). ISSCC, page 178-179. IEEE, (2014)A 33kDMIPS 6.4W Vehicle Communication Gateway Processor Achieving 10Gbps/W Network Routing, 40ms CAN Bus Start-Up and 1.4mW Standby Power., , , , , , , and . ISSCC, page 240-241. IEEE, (2023)A Novel Layout Approach Using Dual Supply Voltage Technique on Body-Tied PD-SOI., , , , and . PATMOS, volume 3254 of Lecture Notes in Computer Science, page 423-432. Springer, (2004)4.5 A 16nm FinFET heterogeneous nona-core SoC complying with ISO26262 ASIL-B: Achieving 10-7 random hardware failures per hour reliability., , , , , , , and . ISSCC, page 80-81. IEEE, (2016)Design Challenges in 3-D SoC Stacked With a 12.8 GB/s TSV Wide I/O DRAM., , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 6 (3): 364-372 (2016)