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Disambiguation of "Garcia-Arias, Angel Lopez"

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Submicrosecond Latency Video Compression in a Low-End FPGA-based System-on-Chip.

, , , , and . FPL, page 355-359. IEEE Computer Society, (2018)

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Ángel López García

Elpidio Lopez Arias

Angel Lopez-Mras

Miguel Angel Vales García

Jesús Ángel Gomollón García

 

Other publications of authors with the same name

Pianissimo: A Sub-mW Class DNN Accelerator With Progressively Adjustable Bit-Precision., , , , , , , , , and . IEEE Access, (2024)Multicoated and Folded Graph Neural Networks with Strong Lottery Tickets., , , , , , , and . CoRR, (2023)Pianissimo: A Sub-mW Class DNN Accelerator with Progressive Bit-by-Bit Datapath Architecture for Adaptive Inference at Edge., , , , , , , , , and . VLSI Technology and Circuits, page 1-2. IEEE, (2023)Submicrosecond Latency Video Compression in a Low-End FPGA-based System-on-Chip., , , , and . FPL, page 355-359. IEEE Computer Society, (2018)Multicoated Supermasks Enhance Hidden Networks., , , , , , , and . ICML, volume 162 of Proceedings of Machine Learning Research, page 17045-17055. PMLR, (2022)Hidden-Fold Networks: Random Recurrent Residuals Using Sparse Supermasks., , , and . BMVC, page 205. BMVA Press, (2021)Recurrent Residual Networks Contain Stronger Lottery Tickets., , , , and . IEEE Access, (2023)Partial Search in a Frozen Network is Enough to Find a Strong Lottery Ticket., , , , , , , , and . CoRR, (2024)Low-Cost Reservoir Computing using Cellular Automata and Random Forests., , and . ISCAS, page 1-5. IEEE, (2020)Amorphica: 4-Replica 512 Fully Connected Spin 336MHz Metamorphic Annealer with Programmable Optimization Strategy and Compressed-Spin-Transfer Multi-Chip Extension., , , , , , , , , and 2 other author(s). ISSCC, page 42-43. IEEE, (2023)