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Disambiguation of "Lee, Chang-Kyo"

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Performance Test of LTE-R Railway Wireless Communication at High-Speed (350 km/h) Environments.

, , , , and . ICUFN, page 637-640. IEEE, (2018)

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Chang-Kyo Jeong

Chong-Kyo Lee

Kyo-Il Lee

Chang-Uh Lee

Lee Chang Huan

 

Other publications of authors with the same name

A 10-Bit 40-MS/s Pipelined ADC With a Wide Range Operating Temperature for WAVE Applications., , and . IEEE Trans. Circuits Syst. II Express Briefs, 61-II (1): 6-10 (2014)Performance Test of LTE-R Railway Wireless Communication at High-Speed (350 km/h) Environments., , , , and . ICUFN, page 637-640. IEEE, (2018)A 550µW 10b 40MS/s SAR ADC with multistep addition-only digital error correction., , , and . CICC, page 1-4. IEEE, (2010)Design of a 1-Volt and µ-power SARADC for Sensor Network Application., , and . ISCAS, page 3852-3855. IEEE, (2007)Interpretation of Impact-Echo Testing Data from a Fire-Damaged Reinforced Concrete Slab Using a Discrete Layered Concrete Damage Model., , , , and . Sensors, 20 (20): 5838 (2020)22.2 An 8.5Gb/s/pin 12Gb-LPDDR5 SDRAM with a Hybrid-Bank Architecture using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a 2nd generation 10nm DRAM Process., , , , , , , , , and 29 other author(s). ISSCC, page 382-384. IEEE, (2020)Dual-loop 2-step ZQ calibration for dedicated power supply voltage in LPDDR4 SDRAM., , , , , , , , , and 25 other author(s). A-SSCC, page 153-156. IEEE, (2017)A 550-μW 10-b 40-MS/s SAR ADC With Multistep Addition-Only Digital Error Correction., , , and . IEEE J. Solid State Circuits, 46 (8): 1881-1892 (2011)A 7.5 Gb/s/pin 8-Gb LPDDR5 SDRAM With Various High-Speed and Low-Power Techniques., , , , , , , , , and 7 other author(s). IEEE J. Solid State Circuits, 55 (1): 157-166 (2020)A sub-0.85V, 6.4GBP/S/Pin TX-Interleaved Transceiver with Fast Wake-Up Time Using 2-Step Charging Control and VOHCalibration in 20NM DRAM Process., , , , , , , , , and 16 other author(s). VLSI Circuits, page 147-148. IEEE, (2018)