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ESD protection design for I/O cells in sub-130-nm CMOS technology with embedded SCR structure., and . ISCAS (2), page 1182-1185. IEEE, (2005)On-chip ESD protection circuit design with novel substrate-triggered SCR device in sub-quarter-micron CMOS process., and . ISCAS (5), page 529-532. IEEE, (2002)Improvement on ESD Robustness of Lateral DMOS in High-voltage CMOS ICs by Body Current Injection., , , , and . ISCAS, page 385-388. IEEE, (2009)Design on mixed-voltage-tolerant I/O interface with novel tracking circuits in a 0.13-µm CMOS technology., and . ISCAS (2), page 577-580. IEEE, (2004)A new Schmitt trigger circuit in a 0.13 µm 1/2.5 V CMOS process to receive 3.3 V input signals., and . ISCAS (2), page 573-576. IEEE, (2004)Anomalous latchup failure induced by on-chip ESD protection circuit in a high-voltage CMOS IC product., , , and . Microelectron. Reliab., 43 (8): 1295-1301 (2003)Failure analysis and solutions to overcome latchup failure event of a power controller IC in bulk CMOS technology., and . Microelectron. Reliab., 46 (7): 1042-1049 (2006)MOS-Bounded Diodes for On-Chip ESD Protection in Deep Submicron CMOS Process., , and . IEICE Trans. Electron., 88-C (3): 429-436 (2005)A CMOS Bandgap Reference Circuit for Sub-1-V Operation without Using Extra Low-Threshold-Voltage Device., , and . IEICE Trans. Electron., 88-C (11): 2150-2155 (2005)A new Schmitt trigger circuit in a 0.13-μm 1/2.5-V CMOS process to receive 3.3-V input signals., and . IEEE Trans. Circuits Syst. II Express Briefs, 52-II (7): 361-365 (2005)