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Architecture-Level Soft Error Analysis: Examining the Limits of Common Assumptions.

, , , and . DSN, page 266-275. IEEE Computer Society, (2007)

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Active Management of Data Caches by Exploiting Reuse Information., , , , and . IEEE Trans. Computers, 48 (11): 1244-1259 (1999)Online Estimation of Architectural Vulnerability Factor for Soft Errors., , , and . ISCA, page 341-352. IEEE Computer Society, (2008)Power management of multi-core chips: Challenges and pitfalls., , , , , , , , , and 1 other author(s). DATE, page 977-982. IEEE, (2012)Exploiting Structural Duplication for Lifetime Reliability Enhancement., , , and . ISCA, page 520-531. IEEE Computer Society, (2005)A Framework for Architecture-Level Lifetime Reliability Modeling., , , , and . DSN, page 534-543. IEEE Computer Society, (2007)On Effective Data Supply For Multi-Issue Processors., , and . ICCD, page 519-528. IEEE Computer Society, (1997)Evaluating the performance of active cache management schemes., , , , and . ICCD, page 368-375. IEEE Computer Society, (1998)Utilizing Reuse Information in Data Cache Management., , , , and . International Conference on Supercomputing, page 449-456. ACM, (1998)Power-efficient, reliable microprocessor architectures: modeling and design methods., , , , , , , , , and 5 other author(s). ACM Great Lakes Symposium on VLSI, page 299-304. ACM, (2010)On High-Bandwidth Data Cache Design for Multi-Issue Processors., , , and . MICRO, page 46-56. ACM/IEEE Computer Society, (1997)