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A 65 nm single stage 28 fJ/cycle 0.12 to 1.2V level-shifter., и . ISCAS, стр. 990-993. IEEE, (2014)3.6 A 60pJ/b 300Mb/s 128×8 Massive MIMO precoder-detector in 28nm FD-SOI., , , и . ISSCC, стр. 60-61. IEEE, (2017)A < 1 pJ sub-VT cardiac event detector in 65 nm LL-HVT CMOS., , и . VLSI-SoC, стр. 253-258. IEEE, (2010)Algorithm and hardware aspects of pre-coding in massive MIMO systems., , , и . ACSSC, стр. 1144-1148. IEEE, (2015)A 65-nm CMOS area optimized de-synchronization flow for sub-VT designs., , , , , и . VLSI-SoC, стр. 380-385. IEEE, (2013)An area efficient single-cycle xVDD sub-Vth on-chip boost scheme in 28 nm FD-SOI., , , , и . A-SSCC, стр. 229-232. IEEE, (2016)Ultra-Low-Power Error Correction Circuits: Technology Scaling and Sub-VT Operation., и . IEEE Trans. Circuits Syst. II Express Briefs, 59-II (12): 913-917 (2012)Benchmarking of Standard-Cell Based Memories in the Sub- VT Domain in 65-nm CMOS Technology., , , и . IEEE J. Emerg. Sel. Topics Circuits Syst., 1 (2): 173-182 (2011)TamaRISC-CS: An ultra-low-power application-specific processor for compressed sensing., , , , , , и . VLSI-SoC, стр. 159-164. IEEE, (2012)A 500 fW/bit 14 fJ/bit-access 4kb standard-cell based sub-VT memory in 65nm CMOS., , , , , и . ESSCIRC, стр. 321-324. IEEE, (2012)