( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
Partitioning Variables across Register Windows to Reduce Spill Code in a Low-Power Processor.

, , , , , , и . IEEE Trans. Computers, 54 (8): 998-1012 (2005)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Elke Guthaus

Matthew Mellon

Matthew David

Olumuyiwa Matthew

Matthew Grum

 

Другие публикации лиц с тем же именем

Current-mode clock distribution., и . ISCAS, стр. 1203-1206. IEEE, (2014)Process-induced skew reduction in nominal zero-skew clock trees., , и . ASP-DAC, стр. 84-89. IEEE, (2006)Non-uniform clock mesh optimization with linear programming buffer insertion., , и . DAC, стр. 74-79. ACM, (2010)CMCS: Current-Mode Clock Synthesis., и . IEEE Trans. Very Large Scale Integr. Syst., 25 (3): 1054-1062 (2017)Dynamic voltage scaling for SEU-tolerance in low-power memories., и . VLSI-SoC, стр. 207-212. IEEE, (2012)High-Performance, Low-Power Resonant Clocking: Embedded tutorial., и . ICCAD, стр. 742-745. ACM, (2012)Partitioning Variables across Register Windows to Reduce Spill Code in a Low-Power Processor., , , , , , и . IEEE Trans. Computers, 54 (8): 998-1012 (2005)VAR-TX: A variability-aware SRAM model for predicting the optimum architecture to achieve minimum access-time for yield enhancement in nano-scaled CMOS., , и . ISQED, стр. 506-515. IEEE, (2012)HCDN: Hybrid-Mode Clock Distribution Networks., и . IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (1): 251-262 (2019)DCMCS: Highly Robust Low-Power Differential Current-Mode Clocking and Synthesis., , , и . IEEE Trans. Very Large Scale Integr. Syst., 26 (10): 2108-2117 (2018)