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Disambiguation of "Shahramian, Shahriar"

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Hardware reduction by combining pipelined A/D conversion and FIR filtering for channel equalization.

, and . ISCAS (3), page 489-492. IEEE, (2004)

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Shahriar Sharafat

Shahriar Rabbanifar

Shahriar Sarami

Shahriar Fakher

Shahriar Fatehi

 

Other publications of authors with the same name

Practical Approaches to Industrializing Near-THz Communication Systems., , , , , , , and . BCICTS, page 5-8. IEEE, (2023)Hardware reduction by combining pipelined A/D conversion and FIR filtering for channel equalization., and . ISCAS (3), page 489-492. IEEE, (2004)A fully integrated scalable W-band phased-array module with integrated antennas, self-alignment and self-test., , , , and . ISSCC, page 74-76. IEEE, (2018)Design Methodology for a 40-GSamples/s Track and Hold Amplifier in 0.18-$muhbox m$SiGe BiCMOS Technology., , and . IEEE J. Solid State Circuits, 41 (10): 2233-2240 (2006)Introduction to the Special Section on the 2018 IEEE BCICTS Conference.. IEEE J. Solid State Circuits, 54 (9): 2359-2360 (2019)Demonstration of 112-Gbit/s optical transmission using 56GBaud PAM-4 driver and clock-and-data recovery ICs., , , , , , , , , and 4 other author(s). ECOC, page 1-3. IEEE, (2015)A 30-GS/sec Track and Hold Amplifier in 0.13-μm CMOS Technology., , and . CICC, page 493-496. IEEE, (2006)A 70-100 GHz Direct-Conversion Transmitter and Receiver Phased Array Chipset Demonstrating 10 Gb/s Wireless Link., , , and . IEEE J. Solid State Circuits, 48 (5): 1113-1125 (2013)A 35-GS/s, 4-Bit Flash ADC With Active Data and Clock Distribution Trees., , and . IEEE J. Solid State Circuits, 44 (6): 1709-1720 (2009)Design of a Dual W- and D-Band PLL., , , , , , and . IEEE J. Solid State Circuits, 46 (5): 1011-1022 (2011)