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Embedded two-rail checkers with on-line testing ability.

, , and . VTS, page 145-150. IEEE Computer Society, (1996)

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Single Output Distributed Two-Rail Checker with Diagnosing Capabilities for Bus Based Self-Checking Architectures., and . J. Electron. Test., 18 (3): 273-283 (2002)Concurrent Checking of Clock Signal Correctness., , and . IEEE Des. Test Comput., 15 (4): 42-48 (1998)CMOS Self Checking Circuits with Faulty Sequential Functional Block., , and . DFT, page 133-141. IEEE Computer Society, (1994)A Highly Testable 1-out-of-3 CMOS Checker., , , and . DFT, page 279-286. IEEE Computer Society, (1993)Implications of Clock Distribution Faults and Issues with Screening Them during Manufacturing Testing., , and . IEEE Trans. Computers, 53 (5): 531-546 (2004)Novel on-chip circuit for jitter testing in high-speed PLLs., , and . IEEE Trans. Instrum. Meas., 54 (5): 1779-1788 (2005)Low-Cost Strategy for Bus Propagation Delay Reduction., , and . J. Electron. Test., 35 (2): 253-260 (2019)High-Performance Robust Latches., , and . IEEE Trans. Computers, 59 (11): 1455-1465 (2010)Low Cost NBTI Degradation Detection and Masking Approaches., , , and . IEEE Trans. Computers, 62 (3): 496-509 (2013)Optimization of error detecting codes for the detection of crosstalk originated errors., and . DATE, page 290-296. IEEE Computer Society, (2001)