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On the in-field functional testing of decode units in pipelined RISC processors.

, , , , , , , and . DFT, page 299-304. IEEE Computer Society, (2014)

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Automatic generation of test sets for SBST of microprocessor IP cores., , , and . SBCCI, page 74-79. ACM, (2005)Evaluating the impact of Permanent Faults in a GPU running a Deep Neural Network., , , , and . ITC-Asia, page 96-101. IEEE, (2022)Functional test generation for DMA controllers., , , , , and . LATW, page 1-6. IEEE, (2010)Investigating the effect of approximate multipliers on the resilience of a systolic array DNN accelerator., , , , , , and . DFT, page 1-6. IEEE, (2023)A Framework for Automated Detection of Power-related Software Errors in Industrial Verification Processes., , , , and . J. Electron. Test., 26 (6): 689-697 (2010)An evolutionary approach to hardware encryption and Trojan-horse mitigation., , , and . DATE, page 1593-1598. IEEE, (2017)An FPGA-based dynamically reconfigurable platform for emulation of permanent faults in ASICs., , , , and . Microelectron. Reliab., (2017)Image Test Libraries for the on-line self-test of functional units in GPUs running CNNs., , , , , , , and . ETS, page 1-6. IEEE, (2023)Coupling EA and high-level metrics for the automatic generation of test blocks for peripheral cores., , , and . GECCO, page 1912-1919. ACM, (2007)On the development of a high-level fault simulator for the analysis of performance faults on speculative modules., , and . LATS, page 1-6. IEEE, (2017)