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A power-predictive environment for fast and power-aware ASIC-based FIR filter design., , , , , и . SBCCI, стр. 168-173. ACM, (2017)Framework-based arithmetic core generation to explore ASIC-based parallel binary multipliers., , , , и . ICECS, стр. 478-481. IEEE, (2017)Low power SATD architecture employing multiple sizes Hadamard Transforms and adder compressors., , , , и . NEWCAS, стр. 277-280. IEEE, (2017)Using adder and subtractor compressors to sum of absolute transformed differences architecture for low-power video encoding., , , , , , , и . ICECS, стр. 490-493. IEEE, (2017)Evaluation of Imprecise Subtractors into Test Zone Search for VVC Encoding., , , и . SBCCI, стр. 1-6. IEEE, (2023)A Hardware-Friendly Fast VVC Test Zone Search Algorithm Using Machine Learning., , , , , , и . LASCAS, стр. 1-5. IEEE, (2024)VVC Interpicture Prediction Using SAD with Imprecise Subtractors: A Quantitative Analysis., , , , и . ICECS 2022, стр. 1-4. IEEE, (2022)HEVC Interpolation Filter Architecture Using Hybrid Encoding Arithmetic Operators., , , , , и . MWSCAS, стр. 331-334. IEEE, (2019)Pruning and approximation of coefficients for power-efficient 2-D Discrete Tchebichef Transform., , , , и . NEWCAS, стр. 25-28. IEEE, (2017)Risk Perception and Misinformation in Brazilian Twitter during COVID-19 Infodemic., , и . ISPA/BDCloud/SocialCom/SustainCom, стр. 435-442. IEEE, (2022)