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Process, Circuit and System Co-optimization of Wafer Level Co-Integrated FinFET with Vertical Nanosheet Selector for STT-MRAM Applications., , , , , , , , , and 2 other author(s). DAC, page 13. ACM, (2019)Exploring Pareto-Optimal Hybrid Main Memory Configurations Using Different Emerging Memories., , , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 70 (2): 733-746 (February 2023)Manufacturable 300mm platform solution for Field-Free Switching SOT-MRAM., , , , , , , , , and 7 other author(s). VLSI Circuits, page 194-. IEEE, (2019)New Memory Technology, Design and Architecture Co-Optimization to Enable Future System Needs.. VLSI-DAT, page 1. IEEE, (2019)Cross-layer design and analysis of a low power, high density STT-MRAM for embedded systems., , , , , , , , , and . ISCAS, page 1-4. IEEE, (2017)Main memory organization trade-offs with DRAM and STT-MRAM options based on gem5-NVMain simulation frameworks., , , , , , , , , and 3 other author(s). DATE, page 103-108. IEEE, (2018)Design Technology co-optimization of 1D-1VCMA to improve read performance for SCM applications., , , , , , and . ISCAS, page 1-5. IEEE, (2023)Liquid Memory and the Future of Data Storage., , , , , , , , , and 6 other author(s). IMW, page 1-4. IEEE, (2022)Impact of Mechanical Stress on the Electrical Performance of 3D NAND., , , , , , and . IRPS, page 1-5. IEEE, (2019)A Smaller, Faster, and More Energy-Efficient Complementary STT-MRAM Cell Uses Three Transistors and a Ground Grid: More Is Actually Less., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 25 (4): 1204-1214 (2017)