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Doped GeSe materials for selector applications., , , , , , , , , and 1 other author(s). ESSDERC, page 168-171. IEEE, (2017)Characterization, Modeling and Test of Synthetic Anti-Ferromagnet Flip Defect in STT-MRAMs., , , , , and . ITC, page 1-10. IEEE, (2020)Enhanced performance and low-power capability of SiGeAsSe-GeSbTe 1S1R phase-change memory operated in bipolar mode., , , , , , , , , and 3 other author(s). VLSI Technology and Circuits, page 312-313. IEEE, (2022)Selective operations of multi-pillar SOT-MRAM for high density and low power embedded memories., , , , , , , , , and . VLSI Technology and Circuits, page 375-376. IEEE, (2022)Device-Aware Test for Back-Hopping Defects in STT-MRAMs., , , , , , , , and . DATE, page 1-6. IEEE, (2023)Modeling and spectroscopy of ovonic threshold switching defects., , , , , , and . IRPS, page 1-5. IEEE, (2021)MTJ degradation in SOT-MRAM by self-heating-induced diffusion., , , , , , , and . IRPS, page 4. IEEE, (2022)Process, Circuit and System Co-optimization of Wafer Level Co-Integrated FinFET with Vertical Nanosheet Selector for STT-MRAM Applications., , , , , , , , , and 2 other author(s). DAC, page 13. ACM, (2019)Towards low damage and fab-compatible top-contacts in MX2 transistors using a combined synchronous pulse atomic layer etch and wet-chemical etch approach., , , , , , , , , and 7 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)Variation-Aware Physics-Based Electromigration Modeling and Experimental Calibration for VLSI Interconnects., , , , , , , and . IRPS, page 1-6. IEEE, (2019)