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Disambiguation of "Belmonte, Attilio"

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Enhanced data integrity of In-Ga-Zn-Oxide based Capacitor-less 2T memory for DRAM applications.

, , , , , , , , , and . ESSDERC, page 275-278. IEEE, (2021)

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Attilio Celio

Walter Belmonte

Fabien Belmonte

Attilio Gambardella

Arturo Belmonte-Pool

 

Other publications of authors with the same name

Enhanced data integrity of In-Ga-Zn-Oxide based Capacitor-less 2T memory for DRAM applications., , , , , , , , , and . ESSDERC, page 275-278. IEEE, (2021)Demonstration of multilevel multiply accumulate operations for AiMC using engineered a-IGZO transistors-based 2T1C gain cell arrays., , , , , , , , and . IMW, page 1-4. IEEE, (2023)Optimization of the write algorithm at low-current (10μA) in Cu/Al2O3-based conductive-bridge RAM., , , , , and . ESSDERC, page 114-117. IEEE, (2015)Conductive filaments multiplicity as a variability factor in CBRAM., , , , , , and . IRPS, page 11. IEEE, (2015)Process-induced charging damage in IGZO nTFTs., , , , , , , , and . IRPS, page 1-8. IEEE, (2021)Ultra-low Leakage IGZO-TFTs with Raised Source/Drain for Vt > 0 V and Ion > 30 µA/µm., , , , , , , , , and 14 other author(s). VLSI Technology and Circuits, page 292-293. IEEE, (2022)Lowest IOFF < 3×10-21 A/μm in capacitorless DRAM achieved by Reactive Ion Etch of IGZO-TFT., , , , , , , , , and 1 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)Device engineering guidelines for performance boost in IGZO front gated TFTs based on defect control., , , , , , , , , and 10 other author(s). ICICDT, page 88. IEEE, (2022)Enhancement of CBRAM performance by controlled formation of a hourglass-shaped filament., , , , , , and . NVMTS, page 1-5. IEEE, (2017)