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Другие публикации лиц с тем же именем

Analyzing testability from behavioral to RT level., , и . ED&TC, стр. 158-165. IEEE Computer Society, (1997)High-level synthesis for easy testability., , и . ED&TC, стр. 198-206. IEEE Computer Society, (1995)New testing procedure for finding insertion sites of stealthy hardware trojans., , , , и . DATE, стр. 776-781. ACM, (2015)A Flip-Flop Matching Engine to Verify Sequential Optimizations., , и . Comput. Artif. Intell., 23 (5): 437-460 (2004)Scan chain encryption for the test, diagnosis and debug of secure circuits., , , , , и . ETS, стр. 1-6. IEEE, (2017)Laser attacks on integrated circuits: From CMOS to FD-SOI., , , , , , , , , и . DTIS, стр. 1-6. IEEE, (2014)A novel hardware logic encryption technique for thwarting illegal overproduction and Hardware Trojans., , , , и . IOLTS, стр. 49-54. IEEE, (2014)Compression-based SoC Test Infrastructures., , и . VLSI-SoC (Selected Papers), том 291 из IFIP, стр. 1-15. Springer, (2007)On Preventing SAT Attack with Decoy Key-Inputs., , , и . ISVLSI, стр. 114-119. IEEE, (2021)An Integrated Validation Environment for Differential Power Analysis., , и . DELTA, стр. 527-532. IEEE Computer Society, (2008)