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Power, Performance, Area and Cost Analysis of Memory-on-Logic Face-to-Face Bonded 3D Processor Designs.

, , , , , , , and . ISLPED, page 1-6. IEEE, (2021)

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Memory Hierarchy Calibration Based on Real Hardware In-order Cores for Accurate Simulation., , , , , and . DATE, page 707-710. IEEE, (2021)Process, Circuit and System Co-optimization of Wafer Level Co-Integrated FinFET with Vertical Nanosheet Selector for STT-MRAM Applications., , , , , , , , , and 2 other author(s). DAC, page 13. ACM, (2019)Analyzing the Electromigration Challenges of Computation in Resistive Memories., , , , and . ITC, page 534-538. IEEE, (2022)Power, Performance, Area and Cost Analysis of Memory-on-Logic Face-to-Face Bonded 3D Processor Designs., , , , , , , and . ISLPED, page 1-6. IEEE, (2021)STT-MRAM Stochastic and Defects-aware DTCO for Last Level Cache at Advanced Process Nodes., , , , , , , , and . ESSDERC, page 97-100. IEEE, (2023)Design Technology co-optimization of 1D-1VCMA to improve read performance for SCM applications., , , , , , and . ISCAS, page 1-5. IEEE, (2023)Beyond RSS: Towards Intelligent Dynamic Memory Management (Work in Progress)., , , , , and . MPLR, page 158-164. ACM, (2023)Enhanced data integrity of In-Ga-Zn-Oxide based Capacitor-less 2T memory for DRAM applications., , , , , , , , , and . ESSDERC, page 275-278. IEEE, (2021)Design exploration of IGZO diode based VCMA array design for Storage Class Memory Applications., , , , , , , and . ESSDERC, page 241-244. IEEE, (2022)AMPeD: An Analytical Model for Performance in Distributed Training of Transformers., , , , , and . ISPASS, page 306-315. IEEE, (2023)