Author of the publication

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

A 0.84ps-LSB 2.47mW time-to-digital converter using charge pump and SAR-ADC., , , and . CICC, page 1-4. IEEE, (2013)An 81.6dB SNDR 15.625MHz BW 3rd Order CT SDM with a True TI NS Quantizer., , , , and . VLSI Technology and Circuits, page 54-55. IEEE, (2022)An Ultra-Low-Voltage 160 MS/s 7 Bit Interpolated Pipeline ADC Using Dynamic Amplifiers., , , , and . IEEE J. Solid State Circuits, 50 (6): 1399-1411 (2015)An 81.6 dB SNDR 15.625 MHz BW Third-Order CT SDM With a True Time-Interleaving Noise-Shaping Quantizer., , , , and . IEEE J. Solid State Circuits, 58 (4): 929-938 (2023)A 50μW 4-channel 83dBA-SNDR Speech Recognition Front-End with Adaptive Beamforming and Feature Extraction., , , , and . CICC, page 1-2. IEEE, (2021)HK386: an x86-compatible 32-bit CISC microprocessor., , , , , , , , , and 2 other author(s). ASP-DAC, page 661-662. IEEE, (1997)6GS/s 8-channel CIC SAR TI-ADC with Neural Network Calibration., , , and . ESSCIRC, page 325-328. IEEE, (2022)A 0.024mm² 84.2dB-SNDR 1MHz-BW 3rd-Order VCO-Based CTDSM with NS-SAR Quantizer (NSQ VCO CTDSM)., , and . VLSI Technology and Circuits, page 1-2. IEEE, (2023)A 150-MS/s Fully Dynamic SAR-Assisted Pipeline ADC Using a Floating Ring Amplifier and Gain-Enhancing Miller Negative-C., , , and . VLSI Technology and Circuits, page 1-2. IEEE, (2023)An 8-bit 20.7 TOPS/W Multi-Level Cell ReRAM-based Compute Engine., , , , , , , , , and 6 other author(s). VLSI Technology and Circuits, page 264-265. IEEE, (2022)