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Disambiguation of "Devadas, Srinivas"

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A Lockdown Technique to Prevent Machine Learning on PUFs for Lightweight Authentication.

, , , , , and . IEEE Trans. Multi Scale Comput. Syst., 2 (3): 146-159 (2016)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Vinay Devadas

Deepika Devadas

Srinivas Jagarlamudi

Srinivas Yarlanki

Girish Srinivas

 

Other publications of authors with the same name

Approaches to Multi-level Sequential Logic Synthesis.. DAC, page 270-276. ACM Press, (1989)A Unified Approach to the Decomposition and Re-Decomposition of Sequential Machines., , and . DAC, page 601-606. IEEE Computer Society Press, (1990)TARDIS: Timestamp based Coherence Algorithm for Distributed Shared Memory., and . CoRR, (2015)Proxy-based security protocols in networked mobile devices., , , , , and . SAC, page 265-272. ACM, (2002)Analytical cache models with applications to cache partitioning., , and . ICS, page 1-12. ACM, (2001)On the verification of sequential machines at differing levels of abstraction., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 7 (6): 713-722 (1988)Event-based verification of synchronous, globally controlled, logic designs against signal flow graphs., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 13 (1): 122-134 (1994)Synthesis of robust delay-fault-testable circuits: practice., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 11 (3): 277-300 (1992)Power estimation methods for sequential logic circuits., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 3 (3): 404-416 (1995)Estimation of power dissipation in CMOS combinational circuits using Boolean function manipulation., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 11 (3): 373-383 (1992)