Author of the publication

temperature closed-loop compensation SoC embedding all-digital clock multiplier and DC-DC converter exploiting FDSOI 28nm back-gate biasing.

S. Clerc, M. Saligane, F. Abouzeid, M. Cochet, J. Daveau, C. Bottoni, D. Bol, J. Vos, D. Zamora, B. Coeffic, D. Soussan, D. Croain, M. Naceur, P. Schamberger, P. Roche, and D. Sylvester. ISSCC, page 1-3. IEEE, (2015)

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Paolo Bottoni

Cyril Bazin

Cyril Grouin

Cyril Mazauric

Cyril Cohen

Other publications of authors with the same name

8.4 A 0.33V/-40°C process/temperature closed-loop compensation SoC embedding all-digital clock multiplier and DC-DC converter exploiting FDSOI 28nm back-gate biasing.S. Clerc, M. Saligane, F. Abouzeid, M. Cochet, J. Daveau, C. Bottoni, D. Bol, J. Vos, D. Zamora, B. Coeffic and 6 other author(s). ISSCC, page 1-3. IEEE, (2015)Design and performance parameters of an ultra-low voltage, single supply 32bit processor implemented in 28nm FDSOI technology.S. Clerc, F. Abouzeid, D. Patel, J. Daveau, C. Bottoni, L. Ciampolini, F. Giner, D. Meyer, R. Wilson, P. Roche and 4 other author(s). ISQED, page 366-370. IEEE, (2015)Frequency and voltage effects on SER on a 65nm Sparc-V8 microprocessor under radiation test.C. Bottoni, B. Coeffic, J. Daveau, G. Gasiot, F. Abouzeid, S. Clerc, L. Naviner, and P. Roche. IRPS, page 12. IEEE, (2015)Partial triplication of a SPARC-V8 microprocessor using fault injection.C. Bottoni, B. Coeffic, J. Daveau, L. Naviner, and P. Roche. LASCAS, page 1-4. IEEE, (2015)28nm FD-SOI technology and design platform for sub-10pJ/cycle and SER-immune 32bits processors.F. Abouzeid, S. Clerc, C. Bottoni, B. Coeffic, J. Daveau, D. Croain, G. Gasiot, D. Soussan, and P. Roche. ESSCIRC, page 108-111. IEEE, (2015)

BibSonomy

Disambiguation of "Bottoni, Cyril"