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temperature closed-loop compensation SoC embedding all-digital clock multiplier and DC-DC converter exploiting FDSOI 28nm back-gate biasing.

S. Clerc, M. Saligane, F. Abouzeid, M. Cochet, J. Daveau, C. Bottoni, D. Bol, J. Vos, D. Zamora, B. Coeffic, D. Soussan, D. Croain, M. Naceur, P. Schamberger, P. Roche, and D. Sylvester. ISSCC, page 1-3. IEEE, (2015)

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Christian Clerc

Hans-Georg Clerc

Gabriele Clerc

André Clerc

Hans Clerck

Other publications of authors with the same name

28nm FD-SOI technology and design platform for sub-10pJ/cycle and SER-immune 32bits processors.F. Abouzeid, S. Clerc, C. Bottoni, B. Coeffic, J. Daveau, D. Croain, G. Gasiot, D. Soussan, and P. Roche. ESSCIRC, page 108-111. IEEE, (2015)30% static power improvement on ARM Cortex®-A53 using static biasing-anticipation.F. Abouzeid, C. Bernicot, S. Clerc, J. Daveau, G. Gasiot, D. Noblet, D. Soussan, and P. Roche. ESSCIRC, page 37-40. IEEE, (2016)A 291nW Real-Time Event-Driven Spectrogram Extraction unit in 28nm FD-SOI CMOS for Keyword Spotting Application.S. Mourrane, B. Larras, S. Clerc, A. Cathelin, and A. Frappé. ESSCIRC, page 341-344. IEEE, (2023)A 0.40pJ/cycle 981 μm2 voltage scalable digital frequency generator for SoC clocking.M. Cochet, S. Clerc, G. Lallement, F. Abouzeid, P. Roche, and J. Autran. A-SSCC, page 69-72. IEEE, (2017)Scalable 0.35 V to 1.2 V SRAM Bitcell Design From 65 nm CMOS to 28 nm FDSOI.F. Abouzeid, A. Bienfait, K. Akyel, A. Feki, S. Clerc, L. Ciampolini, F. Giner, R. Wilson, and P. Roche. IEEE J. Solid State Circuits, 49 (7): 1499-1505 (2014)27.1 A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding FMAX tracking.R. Wilson, E. Beigné, P. Flatresse, A. Valentian, F. Abouzeid, T. Benoist, C. Bernard, S. Bernard, O. Billoint, S. Clerc and 12 other author(s). ISSCC, page 452-453. IEEE, (2014)A 0.32V, 55fJ per bit access energy, CMOS 65nm bit-interleaved SRAM with radiation Soft Error tolerance.S. Clerc, F. Abouzeid, G. Gasiot, D. Gauthier, D. Soussan, and P. Roche. ICICDT, page 1-4. IEEE, (2012)Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs.E. Beigné, A. Valentian, B. Giraud, O. Thomas, T. Benoist, Y. Thonnart, S. Bernard, G. Moritz, O. Billoint, Y. Maneglia and 10 other author(s). DATE, page 613-618. EDA Consortium San Jose, CA, USA / ACM DL, (2013)A 3.0μW@5fps QQVGA Self-Controlled Wake-Up Imager with On-Chip Motion Detection, Auto-Exposure and Object Recognition.A. Verdant, W. Guicquero, N. Royer, G. Moritz, S. Martin, F. Lepin, S. Choisnet, F. Guellec, B. Deschamps, S. Clerc and 1 other author(s). VLSI Circuits, page 1-2. IEEE, (2020)28nm CMOS, energy efficient and variability tolerant, 350mV-to-1.0V, 10MHz/700MHz, 252bits frame error-decoder.F. Abouzeid, S. Clerc, B. Pelloux-Prayer, F. Argoud, and P. Roche. ESSCIRC, page 153-156. IEEE, (2012)

BibSonomy

Disambiguation of "Clerc, Sylvain"