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Disambiguation of "Yaghini, Pooria M."

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Capacitive and Inductive TSV-to-TSV Resilient Approaches for 3D ICs.

, , , , and . IEEE Trans. Computers, 65 (3): 693-705 (2016)

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Minu Pooria

Simon M M Laimer

M. Biswas M. Dam

Marcel M M Kuypers

Bernhard M M Lang

 

Other publications of authors with the same name

Capacitive and Inductive TSV-to-TSV Resilient Approaches for 3D ICs., , , , and . IEEE Trans. Computers, 65 (3): 693-705 (2016)Fault injection-based evaluation of a synchronous NoC router., , , and . IOLTS, page 212-214. IEEE Computer Society, (2009)Capacitive Coupling Mitigation for TSV-based 3D ICs., , and . VTS, page 1-6. IEEE Computer Society, (2015)Investigation of transient fault effects in synchronous and asynchronous Network on Chip router., , , and . J. Syst. Archit., 57 (1): 61-68 (2011)Accurate System-level TSV-to-TSV Capacitive Coupling Fault Model for 3D-NoC., , , and . NOCS, page 3:1-3:8. ACM, (2015)Analytical Fault Tolerance Assessment and Metrics for TSV-Based 3D Network-on-Chip., , , and . IEEE Trans. Computers, 64 (12): 3591-3604 (2015)Investigation of Transient Fault Effects in an Asynchronous NoC Router., , , and . PDP, page 540-545. IEEE Computer Society, (2010)Analytical Reliability Analysis of 3D NoC under TSV Failure., , , and . ACM J. Emerg. Technol. Comput. Syst., 11 (4): 43:1-43:16 (2015)Near Volatile and Non-Volatile Memory Processing in 3D Systems., , , and . IEEE Trans. Emerg. Top. Comput., 10 (3): 1657-1664 (2022)ADVOCAT: Automated deadlock verification for on-chip cache coherence and interconnects., , , and . DATE, page 1640-1645. IEEE, (2016)