From post

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

 

Другие публикации лиц с тем же именем

BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W., , , , , , , , , и 1 other автор(ы). IEEE J. Solid State Circuits, 53 (4): 983-994 (2018)Multicoated Supermasks Enhance Hidden Networks., , , , , , , и . ICML, том 162 из Proceedings of Machine Learning Research, стр. 17045-17055. PMLR, (2022)Exploring optimized accelerator design for binarized convolutional neural networks., , , , , и . IJCNN, стр. 2510-2516. IEEE, (2017)APC-SCA: A Fully-Parallel Annealing Algorithm with Autonomous Pinning Effect Control., , , , , , и . IPDPS Workshops, стр. 414-420. IEEE, (2022)A Hybrid Integer Encoding Method for Obtaining High-Quality Solutions of Quadratic Knapsack Problems on Solid-State Annealers., , , , , , и . IEICE Trans. Inf. Syst., 105-D (12): 2019-2031 (декабря 2022)Edge Inference Engine for Deep & Random Sparse Neural Networks with 4-bit Cartesian-Product MAC Array and Pipelined Activation Aligner., , , , , , и . HCS, стр. 1-21. IEEE, (2021)Hiddenite: 4K-PE Hidden Network Inference 4D-Tensor Engine Exploiting On-Chip Model Construction Achieving 34.8-to-16.0TOPS/W for CIFAR-100 and ImageNet., , , , , , , , и . ISSCC, стр. 1-3. IEEE, (2022)Pianissimo: A Sub-mW Class DNN Accelerator With Progressively Adjustable Bit-Precision., , , , , , , , , и . IEEE Access, (2024)STATICA: A 512-Spin 0.25M-Weight Annealing Processor With an All-Spin-Updates-at-Once Architecture for Combinatorial Optimization With Complete Spin-Spin Interactions., , , , , , , , , и . IEEE J. Solid State Circuits, 56 (1): 165-178 (2021)SPCTRE: sparsity-constrained fully-digital reservoir computing architecture on FPGA., , , и . Int. J. Parallel Emergent Distributed Syst., 39 (2): 197-213 (марта 2024)