From post

копировать удалить добавить публикацию в буфер
Запись сообщества
посмотреть историю данной записи
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A Low-power Star-topology Body Area Network Controller for Periodic Data Monitoring Around and Inside the Human Body.

S. Choi, S. Song, K. Sohn, H. Kim, J. Kim, J. Yoo, и H. Yoo. ISWC, стр. 139-140. IEEE Computer Society, (2006)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Janina Söhn

Gerhard Sohn

Renate Söhn

Martin Sohn

Werner Sohn

Другие публикации лиц с тем же именем

An Architecture of Sparse Length Sum Accelerator in AxDIMM.S. Kang, B. Kim, S. Lee, и K. Sohn. AICAS, стр. 1-4. IEEE, (2022)Hardware Architecture and Software Stack for PIM Based on Commercial DRAM Technology : Industrial Product.S. Lee, S. Kang, J. Lee, H. Kim, E. Lee, S. Seo, H. Yoon, S. Lee, K. Lim, H. Shin и 6 other автор(ы). ISCA, стр. 43-56. IEEE, (2021)22.1 A 1.1V 16GB 640GB/s HBM2E DRAM with a Data-Bus Window-Extension Technique and a Synergetic On-Die ECC Scheme.C. Oh, K. Chun, Y. Byun, Y. Kim, S. Kim, Y. Ryu, J. Park, S. Kim, S. uhn Cha, D. Shin и 25 other автор(ы). ISSCC, стр. 330-332. IEEE, (2020)A 1.2 V 20 nm 307 GB/s HBM DRAM With At-Speed Wafer-Level IO Test Scheme and Adaptive Refresh Considering Temperature Distribution.K. Sohn, W. Yun, R. Oh, C. Oh, S. Seo, M. Park, D. Shin, W. Jung, S. Shin, J. Ryu и 9 other автор(ы). IEEE J. Solid State Circuits, 52 (1): 250-260 (2017)A 0.7-fJ/bit/search 2.2-ns search time hybrid-type TCAM architecture.S. Choi, K. Sohn, и H. Yoo. IEEE J. Solid State Circuits, 40 (1): 254-260 (2005)An Energy-Efficient Design of TSV I/O for HBM With a Data Rate up to 10 Gb/s.J. Kim, T. Kim, J. You, K. Kim, B. Moon, K. Sohn, и S. Jung. IEEE J. Solid State Circuits, 58 (11): 3242-3252 (ноября 2023)Aquabolt-XL HBM2-PIM, LPDDR5-PIM With In-Memory Processing, and AXDIMM With Acceleration Buffer.J. Kim, S. Kang, S. Lee, H. Kim, Y. Ro, S. Lee, D. Wang, J. Choi, J. So, Y. Cho и 4 other автор(ы). IEEE Micro, 42 (3): 20-30 (2022)An FPGA-based RNN-T Inference Accelerator with PIM-HBM.S. Kang, S. Lee, B. Kim, H. Kim, K. Sohn, N. Kim, и E. Lee. FPGA, стр. 146-152. ACM, (2022)Design of non-contact 2Gb/s I/O test methods for high bandwidth memory (HBM).H. Lee, S. Kang, H. Yu, W. Yun, J. Jung, S. Ahn, W. Kim, B. Kil, Y. Sung, S. Shin и 9 other автор(ы). A-SSCC, стр. 169-172. IEEE, (2016)18.2 A 1.2V 20nm 307GB/s HBM DRAM with at-speed wafer-level I/O test scheme and adaptive refresh considering temperature distribution.K. Sohn, W. Yun, R. Oh, C. Oh, S. Seo, M. Park, D. Shin, W. Jung, S. Shin, J. Ryu и 11 other автор(ы). ISSCC, стр. 316-317. IEEE, (2016)

BibSonomy

Disambiguation