( en | de | ru )

 

Disambiguation of "Tsai, Tsung-Yi"

Author of the publication

copydeleteadd this publication to your clipboard
Analysis of Calibrated On-Chip Temperature Sensor With Process Compensation for HV Chips.

, , and . IEEE Trans. Circuits Syst. II Express Briefs, 62-II (3): 217-221 (2015)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Yi-Miau Tsai

Yi-Hsuan Tsai

Tsing-Tshih Tsung

Jieh-Wen Tsung

Wei-Ding Tsai

 

Other publications of authors with the same name

Analysis of Calibrated On-Chip Temperature Sensor With Process Compensation for HV Chips., , and . IEEE Trans. Circuits Syst. II Express Briefs, 62-II (3): 217-221 (2015)74-dBc SFDR 71-MHz Four-Stage Pipeline ROM-Less DDFS Using Factorized Second-Order Parabolic Equations., , , and . IEEE Trans. Very Large Scale Integr. Syst., 27 (10): 2464-2468 (2019)Highly Sensitive FPW-Based Microsystem for Rapid Detection of Tetrahydrocannabinol in Human Urine., , , , , and . Sensors, 17 (12): 2760 (2017)High-Accuracy Impedance Read-out Circuit for BIA-type Biomedical Sensors., , , , , , and . Circuits Syst. Signal Process., 40 (9): 4187-4195 (2021)A Slew Rate Variation Compensated 2× VDD I/O Buffer Using Deterministic P/N-PVT Variation Detection Method., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 66-II (1): 116-120 (2019)500 MHz 90 nm CMOS 2 \(\) VDD Digital Output Buffer Immunity to Process and Voltage Variations., , , and . CSSP, 38 (2): 556-568 (2019)A pipeline ROM-less DDFS using equal-division interpolation., , and . ISOCC, page 19-20. IEEE, (2017)A method of leakage reduction and slew-rate adjustment in 2×VDD output buffer for 28 nm CMOS technology and above., , and . ICICDT, page 1-4. IEEE, (2016)Sampling Rate Enhancement for SAR-ADCs Using Adaptive Reset Approach for FOG Systems., , , and . ASICON, page 1-4. IEEE, (2019)A PVT Validation Phase-Lock Loop with Multi-Band VCO Applied in Closed-Loop FOGs., , , and . ICICDT, page 1-4. IEEE, (2019)