( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
Beyond Ideal DVFS Through Ultra-Fine Grain Vdd-Hopping.

, , , , и . VLSI-SoC (Selected Papers), том 508 из IFIP Advances in Information and Communication Technology, стр. 152-172. Springer, (2016)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Andrea Witzenrath

Risikofaktoren für abdominelle Komplikationen nach kardiopulmonalem Bypass. Uni Erlangen-Nürnberg, (2009)

Andrea Rottach

Analysis of the cell cycle dependent dynamics of Dnmt1 and Np95 in living cells. Uni München, (2009)

Andrea Hruby

Die MAPKKK Bck1p des Zellwand-Integritätssignalwegs in der Bäckerhefe Saccharomyces cerevisiae. Uni Münster, (2009)

Michaela Andrea Fingas

Resultate nach radikaler Prostatektomie bei Patienten mit einem Prostatakarzinom Gleason 7-10. Uni Marburg, (2009)

Andrea Krause

 

Другие публикации лиц с тем же именем

Integer ConvNets on Embedded CPUs: Tools and Performance Assessment on the Cortex-A Cores., , , и . ICECS, стр. 598-601. IEEE, (2019)EAST: Encoding-Aware Sparse Training for Deep Memory Compression of ConvNets., , и . AICAS, стр. 233-237. IEEE, (2020)Reducing leakage power by accounting for temperature inversion dependence in dual-Vt synthesized circuits., , , и . ISLPED, стр. 217-220. ACM, (2008)Adaptive Test-Time Augmentation for Low-Power CPU., , , , и . CoRR, (2021)Design of a Flexible Reactivation Cell for Safe Power-Mode Transition in Power-Gated Circuits., , , , и . IEEE Trans. Circuits Syst. I Regul. Pap., 56-I (9): 1979-1993 (2009)Sub-Row Sleep Transistor Insertion for Concurrent Clock-Gating and Power-Gating., , , , и . PATMOS, том 6951 из Lecture Notes in Computer Science, стр. 214-225. Springer, (2011)Dataflow Restructuring for Active Memory Reduction in Deep Neural Networks., и . DATE, стр. 114-119. IEEE, (2021)Design and Characterization of Analog-to-Digital Converters using Graphene P-N Junctions., , , , и . ACM Great Lakes Symposium on VLSI, стр. 253-258. ACM, (2015)Interactive presentation: Efficient computation of discharge current upper bounds for clustered sleep transistor sizing., , , , , и . DATE, стр. 1544-1549. EDA Consortium, San Jose, CA, USA, (2007)Power modeling and characterization of Graphene-based logic gates., , , и . PATMOS, стр. 223-226. IEEE, (2013)