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Performance of a LU decomposition on a multi-FPGA system compared to a low power commodity microprocessor system., , , and . Scalable Comput. Pract. Exp., (2007)Pattern Recognition Tool to Detect Reconfigurable Patterns in MPEG4 Video Processing., , , , and . IPDPS, IEEE Computer Society, (2002)Resource Estimation and Task Scheduling for Multithreaded Reconfigurable Architectures., , and . ICPADS, page 323-. IEEE Computer Society, (2004)Task Scheduling of Control-Data Flow Graphs for Reconfigurable Architectures., , and . ERSA, page 225-231. CSREA Press, (2004)High Level - Application Analysis Techniques & Architectures - To Explore Design possibilities for Reduced Reconfiguration Area Overheads in FPGAs executing Compute Intensive Applications., and . IPDPS, IEEE Computer Society, (2005)Memory architecture template for Fast Block Matching algorithms on FPGAs., , , and . IPDPS Workshops, page 1-8. IEEE, (2010)Analysis and Design of a Context Adaptable SAD/MSE Architecture., , and . Int. J. Reconfigurable Comput., (2009)Methodology to derive context adaptable architectures for FPGAs., , , , , and . IET Comput. Digit. Tech., 3 (1): 124-141 (2009)Memory support design for LU decomposition on the starbridge hyper-computer., , , and . FPT, page 157-164. IEEE, (2006)PRR-PRR Dynamic Relocation., , and . IEEE Comput. Archit. Lett., 8 (2): 44-47 (2009)