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A 10-Gb/s 6-Vpp differential modulator driver in 65-nm CMOS., , и . ISCAS, стр. 1869-1872. IEEE, (2014)A 0.36 pJ/bit, 0.025 mm2, 12.5 Gb/s Forwarded-Clock Receiver With a Stuck-Free Delay-Locked Loop and a Half-Bit Delay Line in 65-nm CMOS Technology., , , , , и . IEEE Trans. Circuits Syst. I Regul. Pap., 63-I (9): 1393-1403 (2016)A 27.1 mW, 7.5-to-11.1 Gb/s single-loop referenceless CDR with direct Up/dn control., , и . CICC, стр. 1-4. IEEE, (2017)BAG2: A process-portable framework for generator-based AMS circuit design., , , , , , и . CICC, стр. 1-8. IEEE, (2018)A 20 Gb/s 0.4 pJ/b energy-efficient transmitter driver architecture utilizing constant Gm., , , , , , , , и . A-SSCC, стр. 1-4. IEEE, (2015)A Generated Multirate Signal Analysis RISC-V SoC in 16nm FinFET., , , , , , , , , и 21 other автор(ы). A-SSCC, стр. 285-288. IEEE, (2018)A 5-GHz subharmonically injection-locked all-digital PLL with complementary switched injection., , , , , , , , , и . ESSCIRC, стр. 384-387. IEEE, (2015)4.3 An Eight-Core 1.44GHz RISC-V Vector Machine in 16nm FinFET., , , , , , , , , и 2 other автор(ы). ISSCC, стр. 58-60. IEEE, (2021)A Variation-Tolerant, Sneak-Current-Compensated Readout Scheme for Cross-Point Memory Based on Two-Port Sensing Technique., , , и . IEEE Trans. Circuits Syst. II Express Briefs, 65-II (12): 1839-1843 (2018)A Real-Time, 1.89-GHz Bandwidth, 175-kHz Resolution Sparse Spectral Analysis RISC-V SoC in 16-nm FinFET., , , , , , , , , и . IEEE J. Solid State Circuits, 54 (7): 1993-2008 (2019)