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Disambiguation of "Suzuki, Azuma"

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DFT Techniques for Wafer-Level At-Speed Testing of High-Speed SRAMs.

, , , , , , , and . ITC, page 164-169. IEEE Computer Society, (2002)

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Yoko Suzuki

Kentaro Azuma

John Azuma

Shigenobu Suzuki

Seiichi Suzuki

 

Other publications of authors with the same name

A 27% active and 85% standby power reduction in dual-power-supply SRAM using BL power calculator and digitally controllable retention circuit., , , , , , , , , and 1 other author(s). ISSCC, page 320-321. IEEE, (2013)A process-variation-tolerant dual-power-supply SRAM with 0.179µm2 Cell in 40nm CMOS using level-programmable wordline driver., , , , , , , , , and 3 other author(s). ISSCC, page 458-459. IEEE, (2009)DFT Techniques for Wafer-Level At-Speed Testing of High-Speed SRAMs., , , , , , , and . ITC, page 164-169. IEEE Computer Society, (2002)A trimless, 0.5V-1.0V wide voltage operation, high density SRAM macro utilizing dynamic cell stability monitor and multiple memory cell access., , , , , , , , , and 2 other author(s). A-SSCC, page 161-164. IEEE, (2011)A configurable SRAM with constant-negative-level write buffer for low-voltage operation with 0.149µm2 cell in 32nm high-k metal-gate CMOS., , , , , , , , , and 1 other author(s). ISSCC, page 348-349. IEEE, (2010)A 0.7 V Single-Supply SRAM With 0.495 µm2 Cell in 65 nm Technology Utilizing Self-Write-Back Sense Amplifier and Cascaded Bit Line Scheme., , , , , , , , , and . IEEE J. Solid State Circuits, 44 (4): 1192-1198 (2009)