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A 27% active and 85% standby power reduction in dual-power-supply SRAM using BL power calculator and digitally controllable retention circuit.

, , , , , , , , , , и . ISSCC, стр. 320-321. IEEE, (2013)

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Atsushi Imai

Atsushi Imai

Atsushi Yagi

Atsushi Fukui

Atsushi Kambayashi

 

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A 47% access time reduction with a worst-case timing-generation scheme utilizing a statistical method for ultra low voltage SRAMs., , , , , , , и . VLSIC, стр. 100-101. IEEE, (2012)Energy efficiency degradation caused by random variation in low-voltage SRAM and 26% energy reduction by Bitline Amplitude Limiting (BAL) scheme., , , и . A-SSCC, стр. 165-168. IEEE, (2011)7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme., , , , , , , , , и 3 other автор(ы). ISSCC, стр. 132-133. IEEE, (2016)Energy efficiency deterioration by variability in SRAM and circuit techniques for energy saving without voltage reduction., , , , , , , и . ICICDT, стр. 1-4. IEEE, (2012)A 13.8pJ/Access/Mbit SRAM with charge collector circuits for effective use of non-selected bit line charges., , , , , , и . VLSIC, стр. 60-61. IEEE, (2012)A 27% active and 85% standby power reduction in dual-power-supply SRAM using BL power calculator and digitally controllable retention circuit., , , , , , , , , и 1 other автор(ы). ISSCC, стр. 320-321. IEEE, (2013)Session 17 overview: SRAM., и . ISSCC, стр. 304-305. IEEE, (2016)0.5-V, 150-MHz, bulk-CMOS SRAM with suspended bit-line read scheme., , , , и . ESSCIRC, стр. 354-357. IEEE, (2010)The circuit design of the synergistic processor element of a CELL processor., , , , , , , , , и 3 other автор(ы). ICCAD, стр. 111-117. IEEE Computer Society, (2005)A process-variation-tolerant dual-power-supply SRAM with 0.179µm2 Cell in 40nm CMOS using level-programmable wordline driver., , , , , , , , , и 3 other автор(ы). ISSCC, стр. 458-459. IEEE, (2009)