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Extracting Events from Web Documents for Social Media Monitoring Using Structured SVM.

, , , and . IEICE Trans. Inf. Syst., 96-D (6): 1410-1414 (2013)

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A 25 Gb/s Wireline Receiver With Feedforward and Feedback Equalizers at Analog Front-End., , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 69 (2): 404-408 (2022)A 16-Gb/s NRZ Receiver With 0.0019-pJ/bit/dB 1-Tap Charge-Redistribution DFE., , , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 70 (3): 904-908 (March 2023)A 0.83pJ/b 52Gb/s PAM-4 Baud-Rate CDR with Pattern-Based Phase Detector for Short-Reach Applications., , , , , , and . ISSCC, page 118-119. IEEE, (2023)A 1.3-4-GHz Quadrature-Phase Digital DLL Using Sequential Delay Control and Reconfigurable Delay Line., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 56 (6): 1886-1896 (2021)Analysis of a Multiwire, Multilevel, and Symbol Correlation Combination Scheme., , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 69 (8): 3416-3427 (2022)A 1.69-pJ/b 14-Gb/s Digital Sub-Sampling CDR With Combined Adaptive Equalizer and Self-Error Corrector., , , , , , and . IEEE Access, (2021)29.5 12Gb/s over four balanced lines utilizing NRZ braid clock signaling with 100% data payload and spread transition scheme for 8K UHD intra-panel interfaces., , , , , , and . ISSCC, page 490-491. IEEE, (2017)A Single-Ended NRZ Receiver With Gain-Enhanced Active-Inductive CTLE and Reference-Selection DFE for Memory Interfaces., , , , , , , and . IEEE J. Solid State Circuits, 59 (4): 1261-1270 (April 2024)30-Gb/s 1.11-pJ/bit Single-Ended PAM-3 Transceiver for High-Speed Memory Links., , , , , , and . IEEE J. Solid State Circuits, 56 (2): 581-590 (2021)12Gb/s over four balanced lines utilizing NRZ braid clock signaling with 100% data payload and spread transition scheme for 8K UHD intra-panel interface., , and . ASP-DAC, page 287-288. IEEE, (2018)