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Session 8 Overview: Ultra-High-Speed Wireline Wireline Subcommittee.

, , and . ISSCC, page 124-125. IEEE, (2021)

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A 2.6 mW/Gbps 12.5 Gbps RX With 8-Tap Switched-Capacitor DFE in 32 nm CMOS., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 47 (4): 897-910 (2012)Design Techniques for High-Speed Multi-Level Viterbi Detectors and Trellis-Coded-Modulation Decoders., , , , , , , , , and 3 other author(s). IEEE Trans. Circuits Syst. I Regul. Pap., 65-I (10): 3529-3542 (2018)Adaptive high-speed and ultra-low power optical interconnect for data center communications., , , , , , , and . ICTON, page 1-4. IEEE, (2017)Analysis of parameter-independent PLLs with bang-bang phase-detectors., , , and . ICECS, page 299-302. IEEE, (1998)F5: Enabling New System Architectures with 2.5D, 3D, and Chiplets., , , , , and . ISSCC, page 529-532. IEEE, (2021)A 5.7mW/Gb/s 24-to-240Ω 1.6Gb/s thin-oxide DDR transmitter with 1.9-to-7.6V/ns clock-feathering slew-rate control in 22nm CMOS., , , , , , , , and . ISSCC, page 310-311. IEEE, (2013)23.6 A 30Gb/s 0.8pJ/b 14nm FinFET receiver data-path., , , , , , , , , and 1 other author(s). ISSCC, page 408-409. IEEE, (2016)A 24-to-72GS/s 8b time-interleaved SAR ADC with 2.0-to-3.3pJ/conversion and >30dB SNDR at nyquist in 14nm CMOS FinFET., , , , , , , , , and . ISSCC, page 358-360. IEEE, (2018)Active compensation of supply noise for a 5-GHz VCO in 45-nm CMOS SOI technology., and . ISCAS, page 2617-2620. IEEE, (2008)A highly digital 0.5-to-4Gb/s 1.9mW/Gb/s serial-link transceiver using current-recycling in 90nm CMOS., , , , , , and . ISSCC, page 152-154. IEEE, (2011)