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Disambiguation of "Jo, Dong-Shin"

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A 0.6 V 12 b 10 MS/s Low-Noise Asynchronous SAR-Assisted Time-Interleaved SAR (SATI-SAR) ADC.

, , , , , , , , and . IEEE J. Solid State Circuits, 51 (8): 1826-1839 (2016)

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Dong-Shin Shin

Dong Woon Shin

Dong-In Shin

Dong-Ook Shin

Dong-Ill Shin

 

Other publications of authors with the same name

A 9.1-ENOB 6-mW 10-Bit 500-MS/s Pipelined-SAR ADC With Current-Mode Residue Processing in 28-nm CMOS., , , , , and . IEEE J. Solid State Circuits, 54 (9): 2532-2542 (2019)A 65 nm CMOS 7b 2 GS/s 20.7 mW Flash ADC With Cascaded Latch Interpolation., , , , and . IEEE J. Solid State Circuits, 50 (10): 2319-2330 (2015)A 6b 28GS/s Four-channel Time-interleaved Current-Steering DAC with Background Clock Phase Calibration., , , , and . VLSI Circuits, page 138-. IEEE, (2019)26.7 A 2.6b/cycle-architecture-based 10b 1 JGS/s 15.4mW 4×-time-interleaved SAR ADC with a multistep hardware-retirement technique., , , , , , , and . ISSCC, page 1-3. IEEE, (2015)A 40-nm CMOS 7-b 32-GS/s SAR ADC With Background Channel Mismatch Calibration., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 67-II (4): 610-614 (2020)A 65-nm CMOS 6-bit 2.5-GS/s 7.5-mW 8 $\times$ Time-Domain Interpolating Flash ADC With Sequential Slope-Matching Offset Calibration., , , , , and . IEEE J. Solid State Circuits, 54 (1): 288-297 (2019)26.4 A 21fJ/conv-step 9 ENOB 1.6GS/S 2× time-interleaved FATI SAR ADC with background offset and timing-skew calibration in 45nm CMOS., , , , , , , and . ISSCC, page 1-3. IEEE, (2015)A 0.6 V 12 b 10 MS/s Low-Noise Asynchronous SAR-Assisted Time-Interleaved SAR (SATI-SAR) ADC., , , , , , , , and . IEEE J. Solid State Circuits, 51 (8): 1826-1839 (2016)