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A 32 kb 0.35-1.2 V, 50 MHz-2.5 GHz Bit-Interleaved SRAM With 8 T SRAM Cell and Data Dependent Write Assist in 28-nm UTBB-FDSOI CMOS.

A. Grover, G. Visweswaran, C. Parthasarathy, M. Daud, D. Turgis, B. Giraud, J. Noel, I. Panades, G. Moritz, E. Beigné, P. Flatresse, P. Kumar, and S. Azmi. IEEE Trans. Circuits Syst. I Regul. Pap., 64-I (9): 2438-2447 (2017)

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Wahyudi David

Florian Bodo David

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Proposal of a new ultra low leakage 10T sub threshold SRAM bitcell.A. Feki, B. Allard, D. Turgis, J. Lafont, and L. Ciampolini. ISOCC, page 470-474. IEEE, (2012)High-Density 4T SRAM Bitcell in 14-nm 3-D CoolCube Technology Exploiting Assist Techniques.R. Boumchedda, J. Noel, B. Giraud, K. Akyel, M. Brocard, D. Turgis, and E. Beigné. IEEE Trans. Very Large Scale Integr. Syst., 25 (8): 2296-2306 (2017)A 32 kb 0.35-1.2 V, 50 MHz-2.5 GHz Bit-Interleaved SRAM With 8 T SRAM Cell and Data Dependent Write Assist in 28-nm UTBB-FDSOI CMOS.A. Grover, G. Visweswaran, C. Parthasarathy, M. Daud, D. Turgis, B. Giraud, J. Noel, I. Panades, G. Moritz, E. Beigné and 3 other author(s). IEEE Trans. Circuits Syst. I Regul. Pap., 64-I (9): 2438-2447 (2017)Optimization of a voltage sense amplifier operating in ultra wide voltage range with back bias design techniques in 28nm UTBB FD-SOI technology.G. Moritz, B. Giraud, J. Noel, D. Turgis, and A. Grover. ICICDT, page 53-56. IEEE, (2013)27.1 A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding FMAX tracking.R. Wilson, E. Beigné, P. Flatresse, A. Valentian, F. Abouzeid, T. Benoist, C. Bernard, S. Bernard, O. Billoint, S. Clerc and 12 other author(s). ISSCC, page 452-453. IEEE, (2014)Efficient yield estimation through generalized importance sampling with application to NBL-assisted SRAM bitcells.L. Ciampolini, J. Lafont, F. Drissi, J. Morin, D. Turgis, X. Jonsson, C. Desclèves, and J. Nguyen. ICCAD, page 89. ACM, (2016)Impact of Random Telegraph Signals on 6T high-density SRAM in 28nm UTBB FD-SOI.K. Akyel, L. Ciampolini, O. Thomas, D. Turgis, and G. Ghibaudo. ESSDERC, page 94-97. IEEE, (2014)RAPIDO Testing and Modeling of Assisted Write and Read Operations for SRAMs.J. Nguyen, D. Turgis, D. Bonciani, B. Lhomme, Y. Carminati, O. Callen, G. Guirleo, L. Ciampolini, and G. Ghibaudo. NATW, page 28-33. IEEE, (2016)Energy-Efficient 4T SRAM Bitcell with 2T Read-Port for Ultra-Low-Voltage Operations in 28 nm 3D Monolithic CoolCubeTM Technology.R. Boumchedda, J. Noel, B. Giraud, A. Makosiej, M. Rios, E. Esmanhotto, E. Bourde-Cicé, M. Bellet, D. Turgis, and E. Beigné. NANOARCH, page 131-137. ACM, (2018)Improving Ge-rich GST ePCM reliability through BEOL engineering.A. Redaelli, A. Gandolfo, G. Samanni, E. Gomiero, E. Petroni, L. Scotti, A. Lippiello, P. Mattavelli, J. Jasse, D. Codegoni and 27 other author(s). ESSDERC, page 231-234. IEEE, (2021)

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Disambiguation of "Turgis, David"

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A 32 kb 0.35-1.2 V, 50 MHz-2.5 GHz Bit-Interleaved SRAM With 8 T SRAM Cell and Data Dependent Write Assist in 28-nm UTBB-FDSOI CMOS.

Please choose a person to relate this publication to

Wahyudi David

Florian Bodo David

Jens-Ulrich Davids

Joachim David

Heinz David

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Turgis, David"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 32 kb 0.35-1.2 V, 50 MHz-2.5 GHz Bit-Interleaved SRAM With 8 T SRAM Cell and Data Dependent Write Assist in 28-nm UTBB-FDSOI CMOS.

Please choose a person to relate this publication to

Wahyudi David

Florian Bodo David

Jens-Ulrich Davids

Joachim David

Heinz David

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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history of this post
URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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A 32 kb 0.35-1.2 V, 50 MHz-2.5 GHz Bit-Interleaved SRAM With 8 T SRAM Cell and Data Dependent Write Assist in 28-nm UTBB-FDSOI CMOS.