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Disambiguation of "Chen, Jwu-E"

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Impact of Capacitance Correlation on Yield Enhancement of Mixed-Signal/Analog Integrated Circuits.

, , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 27 (11): 2097-2101 (2008)

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Chen Chen

Chen Chen

Shih Chen Chen

Yi-Chen Chen

Chen-Loung Chen

 

Other publications of authors with the same name

Yield-award placement optimization for Switched-Capacitor analog integrated circuits., , , and . SoCC, page 170-173. IEEE, (2011)Placement Optimization for Yield Improvement of Switched-Capacitor Analog Integrated Circuits., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 29 (2): 313-318 (2010)A Multilayer Data Copy Test Data Compression Scheme for Reducing Shifting-in Power for Multiple Scan Design., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 15 (7): 767-776 (2007)Nested Quantization Index Modulation for Reversible Watermarking and Its Application to Healthcare Information Management Systems., , , , and . Comput. Math. Methods Medicine, (2012)Automatic Inspection for Wafer Defect Pattern Recognition with Unsupervised Clustering., , , , , , , , , and 2 other author(s). ETS, page 1-2. IEEE, (2021)Application of Three-Repetition Tests Scheme to Improve Integrated Circuits Test Quality to Near-Zero Defect., and . Sensors, 22 (11): 4158 (2022)Fanout fault analysis for digital logic circuits., , , and . Asian Test Symposium, page 33-39. IEEE Computer Society, (1995)Is IDDQ testing not applicable for deep submicron VLSI in year 2011?, , , and . Asian Test Symposium, page 338-343. IEEE Computer Society, (2000)Adaptive Encoding Scheme for Test Volume/Time Reduction in SoC Scan Testing., , and . Asian Test Symposium, page 324-329. IEEE Computer Society, (2005)Fault Analysis on Two-Level (K+1)-Valued Logic Circuits., , and . ISMVL, page 181-188. IEEE Computer Society, (1992)