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IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management.

P. Vivet, E. Guthmuller, Y. Thonnart, G. Pillonnet, C. Tortolero, I. Miro-Panades, G. Moritz, J. Durupt, C. Bernard, D. Varreau, J. Pontes, S. Thuries, D. Coriat, M. Harrand, D. Dutoit, D. Lattard, L. Arnaud, J. Charbonnier, P. Coudrain, A. Garnier, F. Berger, A. Gueugnot, A. Greiner, Q. Meunier, A. Farcy, A. Arriordaz, S. Cheramy, and F. Clermidy. IEEE J. Solid State Circuits, 56 (1): 79-97 (2021)

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César Rose

César Miñambres

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2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm2 Inter-Chiplet Interconnects and 156mW/mm2@ 82%-Peak-Efficiency DC-DC Converters.P. Vivet, E. Guthmuller, Y. Thonnart, G. Pillonnet, G. Moritz, I. Miro-Panades, C. Tortolero, J. Durupt, C. Bernard, D. Varreau and 18 other author(s). ISSCC, page 46-48. IEEE, (2020)Introduction of Fault-Tolerance Mechanisms for Permanent Failures in Coherent Shared-Memory Many-Core Architectures. (Introduction de mécanismes de tolérance aux pannes franches dans les architectures de processeur « many-core » à mémoire partagée cohérente).C. Tortolero. Pierre and Marie Curie University, Paris, France, (2015)Accelerating Variants of the Conjugate Gradient with the Variable Precision Processor.Y. Durand, E. Guthmuller, C. Tortolero, J. Fereyre, A. Bocco, and R. Alidori. ARITH, page 51-57. IEEE, (2022)IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management.P. Vivet, E. Guthmuller, Y. Thonnart, G. Pillonnet, C. Tortolero, I. Miro-Panades, G. Moritz, J. Durupt, C. Bernard, D. Varreau and 18 other author(s). IEEE J. Solid State Circuits, 56 (1): 79-97 (2021)POPSTAR: a Robust Modular Optical NoC Architecture for Chiplet-based 3D Integrated Systems.Y. Thonnart, S. Bernabé, J. Charbonnier, C. Bernard, D. Coriat, C. Tortolero, P. Tissier, B. Charbonnier, S. Malhouitre, D. Saint-Patrice and 5 other author(s). DATE, page 1456-1461. IEEE, (2020)Storage Class Memory with Computing Row Buffer: A Design Space Exploration.V. Egloff, J. Noel, M. Kooli, B. Giraud, L. Ciampolini, R. Gauchi, C. Tortolero, E. Guthmuller, M. Moreau, and J. Portal. DATE, page 1-6. IEEE, (2021)HPDcache: Open-Source High-Performance L1 Data Cache for RISC-V Cores.C. Tortolero. CF, page 377-378. ACM, (2023)WAVES: Wavelength Selection for Power-Efficient 2.5D-Integrated Photonic NoCs.A. Narayan, Y. Thonnart, P. Vivet, C. Tortolero, and A. Coskun. DATE, page 516-521. IEEE, (2019)

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Disambiguation of "Tortolero, César Fuguet"

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IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management.

Please choose a person to relate this publication to

César Rose

César Miñambres

César Collazo

César Moura

César Bernardini

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Tortolero, César Fuguet"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management.

Please choose a person to relate this publication to

César Rose

César Miñambres

César Collazo

César Moura

César Bernardini

Other publications of authors with the same name

Disambiguation

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URL
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IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management.