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mm2@ 82%-Peak-Efficiency DC-DC Converters.

P. Vivet, E. Guthmuller, Y. Thonnart, G. Pillonnet, G. Moritz, I. Miro-Panades, C. Tortolero, J. Durupt, C. Bernard, D. Varreau, J. Pontes, S. Thuries, D. Coriat, M. Harrand, D. Dutoit, D. Lattard, L. Arnaud, J. Charbonnier, P. Coudrain, A. Garnier, F. Berger, A. Gueugnot, A. Greiner, Q. Meunier, A. Farcy, A. Arriordaz, S. Cheramy, and F. Clermidy. ISSCC, page 46-48. IEEE, (2020)

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Damien Vivet

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Pascal Fuchshuber

Other publications of authors with the same name

Reconfigurable tiles of computing-in-memory SRAM architecture for scalable vectorization.R. Gauchi, V. Egloff, M. Kooli, J. Noël, B. Giraud, P. Vivet, S. Mitra, and H. Charles. ISLPED, page 121-126. ACM, (2020)A fully integrated power supply unit for fine grain power management application to embedded Low Voltage SRAMs.E. Beigné, F. Clermidy, S. Miermont, A. Valentian, P. Vivet, S. Barasinski, F. Blisson, N. Kohli, and S. Kumar. ESSCIRC, page 138-141. IEEE, (2008)Thermal performance of CoolCube™ monolithic and TSV-based 3D integration processes.C. Santos, P. Vivet, S. Thuries, O. Billoint, J. Colonna, P. Coudrain, and L. Wang. 3DIC, page 1-5. IEEE, (2016)3D NoC using through silicon Via: An asynchronous implementation.P. Vivet, D. Dutoit, Y. Thonnart, and F. Clermidy. VLSI-SoC, page 232-237. IEEE, (2011)Fast and accurate power annotated simulation: Application to a many-core architecture.T. Ducroux, G. Haugou, V. Risson, and P. Vivet. PATMOS, page 191-198. IEEE, (2013)2D to 3D Test Pattern Retargeting Using IEEE P1687 Based 3D DFT Architectures.Y. Fkih, P. Vivet, B. Rouzeyre, M. Flottes, G. Natale, and J. Schloeffel. ISVLSI, page 386-391. IEEE Computer Society, (2014)An Asynchronous Power Aware and Adaptive NoC Based Circuit.E. Beigné, F. Clermidy, H. Lhermet, S. Miermont, Y. Thonnart, X. Tran, A. Valentian, D. Varreau, P. Vivet, X. Popon and 1 other author(s). IEEE J. Solid State Circuits, 44 (4): 1167-1177 (2009)Experimental Insights Into Thermal Dissipation in TSV-Based 3-D Integrated Circuits.P. Coudrain, P. Souare, R. Prieto, V. Fiori, A. Farcy, L. Pailleur, J. Colonna, C. Santos, P. Vivet, M. Jamaa and 6 other author(s). IEEE Des. Test, 33 (3): 21-36 (2016)On-line Power Optimization of Data Flow Multi-Core Architecture Based on Vdd-Hopping for Local Dynamic Voltage and Frequency Scaling.P. Vivet, E. Beigné, H. Lebreton, and N. Zergainoh. J. Low Power Electron., 7 (2): 265-273 (2011)WAVES: Wavelength Selection for Power-Efficient 2.5D-Integrated Photonic NoCs.A. Narayan, Y. Thonnart, P. Vivet, C. Tortolero, and A. Coskun. DATE, page 516-521. IEEE, (2019)

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