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IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management.

P. Vivet, E. Guthmuller, Y. Thonnart, G. Pillonnet, C. Tortolero, I. Miro-Panades, G. Moritz, J. Durupt, C. Bernard, D. Varreau, J. Pontes, S. Thuries, D. Coriat, M. Harrand, D. Dutoit, D. Lattard, L. Arnaud, J. Charbonnier, P. Coudrain, A. Garnier, F. Berger, A. Gueugnot, A. Greiner, Q. Meunier, A. Farcy, A. Arriordaz, S. Cheramy, and F. Clermidy. IEEE J. Solid State Circuits, 56 (1): 79-97 (2021)

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Nicolas Jeanvoine

Plasma-material interaction and electrode degradation in high voltage ignition dischargesN. Jeanvoine. Uni Saarbrücken, (2009)

Johann Jeanson

Helga Jeanblanc

Marc Jean-Richard-dit-Bressel

Stéphane Jean

Other publications of authors with the same name

Design-for-test approach of an asynchronous network-on-chip architecture and its associated test pattern generation and application.X. Tran, Y. Thonnart, J. Durupt, V. Beroulle, and C. Robach. IET Comput. Digit. Tech., 3 (5): 487-500 (2009)Test Solutions for High Density 3D-IC Interconnects - Focus on SRAM-on-Logic Partitioning.I. Jani, D. Lattard, P. Vivet, J. Durupt, S. Thuries, and E. Beigné. ETS, page 1-2. IEEE, (2019)Experimental multiprocessor architecture dedicated for solving 3D PDEs.J. Libs, B. Siaud, J. Durupt, B. Boutherin, G. Jacquemod, and M. Helley. PDP, page 71-77. IEEE, (1993)IJTAG supported 3D DFT using chiplet-footprints for testing multi-chips active interposer system.J. Durupt, P. Vivet, and J. Schloeffel. ETS, page 1-6. IEEE, (2016)IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management.P. Vivet, E. Guthmuller, Y. Thonnart, G. Pillonnet, C. Tortolero, I. Miro-Panades, G. Moritz, J. Durupt, C. Bernard, D. Varreau and 18 other author(s). IEEE J. Solid State Circuits, 56 (1): 79-97 (2021)An Ultra Low Power SoC for 2.4GHz IEEE802.15.4 wireless communications.C. Bernier, F. Hameau, G. Billiot, E. de Foucauld, S. Robinet, D. Lattard, J. Durupt, F. Dehmas, L. Ouvry, and P. Vincent. ESSCIRC, page 426-429. IEEE, (2008)2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm2 Inter-Chiplet Interconnects and 156mW/mm2@ 82%-Peak-Efficiency DC-DC Converters.P. Vivet, E. Guthmuller, Y. Thonnart, G. Pillonnet, G. Moritz, I. Miro-Panades, C. Tortolero, J. Durupt, C. Bernard, D. Varreau and 18 other author(s). ISSCC, page 46-48. IEEE, (2020)

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Disambiguation of "Durupt, Jean"

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IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management.

Please choose a person to relate this publication to

Nicolas Jeanvoine

Johann Jeanson

Helga Jeanblanc

Marc Jean-Richard-dit-Bressel

Stéphane Jean

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Durupt, Jean"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management.

Please choose a person to relate this publication to

Nicolas Jeanvoine

Johann Jeanson

Helga Jeanblanc

Marc Jean-Richard-dit-Bressel

Stéphane Jean

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management.