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Design for Delay Fault Testability of Dual Circuits Using Master and Slave Scan Paths., , and . IEICE Trans. Inf. Syst., 92-D (3): 433-442 (2009)Design for Delay Fault Testability of 2-Rail Logic Circuits., , and . IEICE Trans. Inf. Syst., 92-D (2): 336-341 (2009)An Analysis of Stochastic Self-Calibration of TDC Using Two Ring Oscillators., , , , , and . Asian Test Symposium, page 140-146. IEEE Computer Society, (2013)A Delay Measurement Technique Using Signature Registers., , , , and . Asian Test Symposium, page 157-162. IEEE Computer Society, (2009)An On-Chip Delay Measurement Technique Using Signature Registers for Small-Delay Defect Detection., , and . IEEE Trans. Very Large Scale Integr. Syst., 20 (5): 804-817 (2012)Revisit to Histogram Method for ADC Linearity Test: Examination of Input Signal and Ratio of Input and Sampling Frequencies., , , , , , , , , and 2 other author(s). J. Electron. Test., 38 (1): 21-38 (2022)Design of On-Line Testing for SoC with IEEE P1500 Compliant Cores Using Reconfigurable Hardware and Scan Shift., , and . IOLTS, page 203-204. IEEE Computer Society, (2005)Innovative Practices Track: Innovative Analog Circuit Testing Technologies., , , , , , , , , and 8 other author(s). VTS, page 1. IEEE, (2022)Built-In Self-Test for PEs of Coarse Grained Dynamically Reconfigurable Devices., and . ETS, page 69-74. IEEE Computer Society, (2006)A Small Chip Area Stochastic Calibration for TDC Using Ring Oscillator., , , , , , and . J. Electron. Test., 30 (6): 653-663 (2014)