( en | de | ru )

 

Disambiguation of "Gurumani, Swathi T."

Author of the publication

copydeleteadd this publication to your clipboard
High Level Synthesis of Complex Applications: An H.264 Video Decoder.

, , , , , and . FPGA, page 224-233. ACM, (2016)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

T Peters

T Frieberg

T Weber

T Hollemann

T Fauster

 

Other publications of authors with the same name

FCUDA-NoC: A Scalable and Efficient Network-on-Chip Implementation for the CUDA-to-FPGA Flow., , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (6): 2220-2233 (2016)Platform choices and design demands for IoT platforms: cost, power, and performance tradeoffs., , , , , and . IET Cyper-Phys. Syst.: Theory & Appl., 1 (1): 70-77 (2016)Fast and effective placement and routing directed high-level synthesis for FPGAs., , , and . FPGA, page 1-10. ACM, (2014)High-level synthesis of multiple dependent CUDA kernels on FPGA., , , , and . ASP-DAC, page 305-312. IEEE, (2013)FCUDA-HB: Hierarchical and Scalable Bus Architecture Generation on FPGAs With the FCUDA Flow., , , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 35 (12): 2032-2045 (2016)AutoSLIDE: Automatic Source-Level Instrumentation and Debugging for HLS., , , and . FCCM, page 127-130. IEEE Computer Society, (2016)Integrated CUDA-to-FPGA Synthesis with Network-on-Chip., , , , , and . FCCM, page 21-24. IEEE Computer Society, (2014)Debugging and verifying SoC designs through effective cross-layer hardware-software co-simulation., , , , , and . DAC, page 7:1-7:6. ACM, (2016)High-level synthesis with behavioral level multi-cycle path analysis., , , , and . FPL, page 1-8. IEEE, (2013)Behavioral-level IP integration in high-level synthesis., , , and . FPT, page 172-175. IEEE, (2015)